MC68336/376
MOTOROLA
USER’S MANUAL
iii
Paragraph
Title
Page
SECTION 1 INTRODUCTION
SECTION 2 NOMENCLATURE
2.1
Symbols and Operators ............................................................................. 2-1
2.2
CPU32 Registers ....................................................................................... 2-2
2.3
Pin and Signal Mnemonics ........................................................................ 2-2
2.4
Register Mnemonics .................................................................................. 2-4
2.5
Conventions .............................................................................................. 2-8
SECTION 3 OVERVIEW
3.1
MCU Features ........................................................................................... 3-1
3.1.1
Central Processing Unit (CPU32) ...................................................... 3-1
3.1.2
System Integration Module (SIM) ...................................................... 3-1
3.1.3
Standby RAM Module (SRAM) .......................................................... 3-1
3.1.4
Masked ROM Module (MRM) ............................................................ 3-1
3.1.5
10-Bit Queued Analog-to-Digital Converter (QADC) ......................... 3-2
3.1.6
Queued Serial Module (QSM) ........................................................... 3-2
3.1.7
Configurable Timer Module Version 4 (CTM4) .................................. 3-2
3.1.8
Time Processor Unit (TPU) ............................................................... 3-2
3.1.9
Static RAM Module with TPU Emulation Capability (TPURAM) ........ 3-2
3.1.10
CAN 2.0B Controller Module (TouCAN) ............................................ 3-3
3.2
Intermodule Bus ........................................................................................ 3-3
3.3
System Block Diagram and Pin Assignment Diagrams ............................. 3-3
3.4
Pin Descriptions ........................................................................................ 3-6
3.5
Signal Descriptions .................................................................................... 3-9
3.6
Internal Register Map .............................................................................. 3-13
3.7
Address Space Maps .............................................................................. 3-14
SECTION 4 CENTRAL PROCESSOR UNIT
4.1
General ...................................................................................................... 4-1
4.2
CPU32 Registers ....................................................................................... 4-2
4.2.1
Data Registers ................................................................................... 4-4
4.2.2
Address Registers ............................................................................. 4-5
4.2.3
Program Counter ............................................................................... 4-6
4.2.4
Control Registers ............................................................................... 4-6
4.2.4.1
Status Register .......................................................................... 4-6
4.2.4.2
Alternate Function Code Registers ........................................... 4-7
4.2.5
Vector Base Register (VBR) .............................................................. 4-7
4.3
Memory Organization ................................................................................ 4-7
TABLE OF CONTENTS
336376UMBook Page iii Friday, November 15, 1996 2:09 PM