MC68336/376
MOTOROLA
USER’S MANUAL
xvii
Figure
Title
Page
3-1
MC68336/376 Block Diagram ........................................................................ 3-4
3-2
MC68336 Pin Assignments for 160-Pin Package .......................................... 3-5
3-3
MC68376 Pin Assignments for 160-Pin Package .......................................... 3-6
3-4
MC68336/376 Address Map ......................................................................... 3-13
3-5
Overall Memory Map .................................................................................... 3-15
3-6
Separate Supervisor and User Space Map .................................................. 3-16
3-7
Supervisor Space (Separate Program/Data Space) Map ............................ 3-17
3-8
User Space (Separate Program/Data Space) Map ...................................... 3-18
4-1
CPU32 Block Diagram ................................................................................... 4-2
4-2
User Programming Model .............................................................................. 4-3
4-3
Supervisor Programming Model Supplement ................................................. 4-4
4-4
Data Organization in Data Registers .............................................................. 4-5
4-5
Address Organization in Address Registers ................................................... 4-6
4-6
Memory Operand Addressing ........................................................................ 4-8
4-7
Loop Mode Instruction Sequence ................................................................. 4-15
4-8
Common In-Circuit Emulator Diagram ......................................................... 4-19
4-9
Bus State Analyzer Configuration ................................................................ 4-19
4-10
Debug Serial I/O Block Diagram .................................................................. 4-24
4-11
BDM Serial Data Word ................................................................................. 4-25
4-12
BDM Connector Pinout ................................................................................. 4-25
5-1
System Integration Module Block Diagram .................................................... 5-2
5-2
System Clock Block Diagram ......................................................................... 5-4
5-3
System Clock Oscillator Circuit ...................................................................... 5-5
5-4
System Clock Filter Networks ........................................................................ 5-6
5-5
LPSTOP Flowchart ....................................................................................... 5-13
5-6
System Protection Block .............................................................................. 5-14
5-7
Periodic Interrupt Timer and Software Watchdog Timer .............................. 5-17
5-8
MCU Basic System ...................................................................................... 5-20
5-9
Operand Byte Order ..................................................................................... 5-25
5-10
Word Read Cycle Flowchart ......................................................................... 5-28
5-11
Write Cycle Flowchart .................................................................................. 5-29
5-12
CPU Space Address Encoding .................................................................... 5-31
5-13
Breakpoint Operation Flowchart ................................................................... 5-33
5-14
LPSTOP Interrupt Mask Level ...................................................................... 5-34
5-15
Bus Arbitration Flowchart for Single Request ............................................... 5-39
5-16
Preferred Circuit for Data Bus Mode Select Conditioning ............................ 5-43
5-17
Alternate Circuit for Data Bus Mode Select Conditioning ............................. 5-44
5-18
Power-On Reset ........................................................................................... 5-49
5-19
Basic MCU System ...................................................................................... 5-55
5-20
Chip-Select Circuit Block Diagram ............................................................... 5-56
5-21
CPU Space Encoding for Interrupt Acknowledge ......................................... 5-61
LIST OF ILLUSTRATIONS
336376UMBook Page xvii Friday, November 15, 1996 2:09 PM