Multi-Master IIC Interface (MMIIC)
Data Sheet
MC68HC908SR12MC68HC08SR12 — Rev. 5.0
292
Multi-Master IIC Interface (MMIIC)
Freescale Semiconductor
17.9.1
17.9.2
17.9.3
17.9.4
17.9.5
17.9.6
17.9.7
Quick Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
Send Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
Receive Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
Write Byte/Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
Read Byte/Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
Process Call. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
17.10 SMBus Protocol Implementation . . . . . . . . . . . . . . . . . . . . . .316
17.2 Introduction
The multi-master IIC (MMIIC) interface is a two wire, bidirectional serial
bus which provides a simple, efficient way for data exchange between
devices. The interface is designed for internal serial communication
between the MCU and other IIC devices. It has hardware generated
START and STOP signals; and byte by byte interrupt driven software
algorithm.
This bus is suitable for applications which need frequent
communications over a short distance between a number of devices. It
also provides a flexibility that allows additional devices to be connected
to the bus. The maximum data rate is 100k-bps, and the maximum
communication distance and number of devices that can be connected
is limited by a maximum bus capacitance of 400pF.
This MMIIC interface is also SMBus (System Management Bus) version
1.0 and 1.1 compatible, with hardware cyclic redundancy code (CRC)
generation, making it suitable for smart battery applications.
For connection flexibility, two channels are available:
Channel 0 — SDA0 and SCL0
Channel 1 — SDA1 and SCL1
The two channels are multiplexed; only one channel is active at any one
time.