
Multi-Master IIC Interface (MMIIC)
MMIIC I/O Registers
MC68HC908SR12MC68HC08SR12 — Rev. 5.0
Data Sheet
Freescale Semiconductor
Multi-Master IIC Interface (MMIIC)
305
17.7.4 MMIIC Status Register (MMSR)
MMRXIF — MMIIC Receive Interrupt Flag
This flag is set after the data receive register (MMDRR) is loaded with
a new received data. Once the MMDRR is loaded with received data,
no more received data can be loaded to the MMDRR register until the
CPU reads the data from the MMDRR to clear MMRXBF flag.
MMRXIF generates an interrupt request to CPU if the MMIEN bit in
MMCR is also set. This bit is cleared by writing "0" to it or by reset; or
when the MMEN = 0.
1 = New data in data receive register (MMDRR)
0 = No data received
MMTXIF — MMIIC Transmit Interrupt Flag
This flag is set when data in the data transmit register (MMDTR) is
downloaded to the output circuit, and that new data can be written to
the MMDTR. MMTXIF generates an interrupt request to CPU if the
MMIEN bit in MMCR is also set. This bit is cleared by writing "0" to it
or when the MMEN = 0.
1 = Data transfer completed
0 = Data transfer in progress
MMATCH — MMIIC Address Match Flag
This flag is set when the received data in the data receive register
(MMDRR) is a calling address which matches with the address or its
extended addresses (MMEXTAD = 1) specified in the address
register (MMADR). The MMATCH flag is set at the 9th clock of the
calling address and will be cleared on the 9th clock of the next
receiving data. Note: slave transmits do not clear MMATCH.
Address:
$004B
Bit 7
6
5
4
3
2
1
Bit 0
Read: MMRXIF
MMTXIF MMATCH MMSRW MMRXAK
MMCRCBF
MMTXBE MMRXBF
Write:
0
0
Reset:
0
0
0
0
1
0
1
0
=Unimplemented
Figure 17-7. MMIIC Status Register (MMSR)