
Configuration and Mask Option
Data Sheet
MC68HC908SR12MC68HC08SR12 — Rev. 5.0
76
Configuration and Mask Option Registers (CONFIG & MOR) Freescale Semiconductor
LVIRSTD — LVI Reset Disable
LVIRSTD disables the reset signal from the LVI module. (See
Section 22. Low-Voltage Inhibit (LVI)
.)
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. (See
Section 22. Low-Voltage
Inhibit (LVI)
.)
1 = LVI module power disabled
0 = LVI module power enabled
LVI5OR3 — LVI 5V or 3V Operating Mode
LVI5OR3 selects the voltage operating mode of the LVI module. (See
Section 22. Low-Voltage Inhibit (LVI)
.) The voltage mode selected
for the LVI should match the operating V
DD
.
See
Section 24.
Electrical Specifications
for the LVI voltage trip points for each of
the modes.
1 = LVI operates in 5V mode
0 = LVI operates in 3V mode
SSREC — Short Stop Recovery
SSREC enables the CPU to exit stop mode with a delay of 32 ICLK
cycles instead of a 4096 ICLK cycle delay.
1 = Stop mode recovery after 32 ICLK cycles
0 = Stop mode recovery after 4096 ICLK cycles
NOTE:
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, and it is disabled during stop mode
(STOP_XCLKEN=0), do not set the SSREC bit.
NOTE:
When the LVI is disabled in stop mode (LVISTOP=0), the system
stabilization time for long stop recovery (4096 ICLK cycles) gives a delay
longer than the LVI’s turn-on time. There is no period where the MCU is
not protected from a low power condition. However, when using the
short stop recovery configuration option, the 32 ICLK delay is less than
the LVI’s turn-on time and there exists a period in start-up where the LVI
is not protecting the MCU.