
iii
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
4.10
Port G ...........................................................................................................
4-8
4.10.1
Data Register (PORTG) .........................................................................
4-9
4.10.2
Data Direction Register (DDRG) ............................................................
4-9
4.11
Port H ...........................................................................................................
4-9
4.11.1
Data Register (PORTH) .........................................................................
4-10
4.11.2
Data Direction Register (DDRH) ............................................................
4-10
4.12
Port J ............................................................................................................
4-11
4.12.1
Data Register (PORTJ) .........................................................................
4-11
4.12.2
Data Direction Register (DDRJ) ............................................................
4-11
4.13
Expanded Bus (Ports B, C, F) ......................................................................
4-12
4.13.1
R/W ........................................................................................................
4-12
4.13.2
Memory Ready (MRDY) .........................................................................
4-13
4.13.3
Options Register 2 (OPT2) .....................................................................
4-13
Section 5
Resets, Interrupts and Low Power Modes
5.1
Resets ..........................................................................................................
5-1
5.1.1
RESET Pin .............................................................................................
5-1
5.1.2
Power-on-reset (POR) ............................................................................
5-1
5.1.3
Computer Operating Properly (COP) Reset ...........................................
5-2
5.1.4
Clock Monitor Reset ...............................................................................
5-2
5.1.5
Configuration Options Register (OPTION) .............................................
5-3
5.1.6
State After Reset ....................................................................................
5-4
5.2
Interrupts ......................................................................................................
5-6
5.2.1
Interrupt Vector Assignments .................................................................
5-6
5.2.2
Software Interrupt (SWI) .........................................................................
5-8
5.2.3
Illegal Opcode Trap ................................................................................
5-8
5.2.4
Real Time Interrupt .................................................................................
5-8
5.2.5
Interrupt Mask Bits in Condition Code Register .....................................
5-9
5.2.6
Priority and Masking Structure ...............................................................
5-9
5.2.7
“Highest Priority I” Interrupt and Miscellaneous Register (HPRIO) ........
5-15
5.3
Low Power Modes .......................................................................................
5-17
5.3.1
WAIT ......................................................................................................
5-17
5.3.2
STOP ......................................................................................................
5-17
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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