
xii
13-1
Test Methods ...............................................................................................
13-4
13-2
Run IDD vs Bus Frequency (Single Chip Mode – 4.5V, 5.5V) .....................
13-5
13-3
Run IDD vs Bus Frequency (Expanded Mode – 4.5V, 5.5V) .......................
13-5
13-4
Wait IDD vs Bus Frequency (Single Chip Mode – 4.5V, 5.5V) ....................
13-6
13-5
Wait IDD vs Bus Frequency (Expanded Mode – 4.5V, 5.5V) ......................
13-6
POR External RESET Timing Diagram ........................................................
13-8
13-7
STOP Recovery Timing Diagram .................................................................
13-8
WAIT Recovery from Interrupt Timing Diagram ...........................................
13-9
Interrupt Timing Diagram .............................................................................
13-9
13-10
Memory Ready Timing Diagram ..................................................................
13-10
13-11
Entering HALT .............................................................................................
13-10
13-12
Exiting HALT ................................................................................................
13-11
13-13
Port Write Timing Diagram ...........................................................................
13-12
13-14
Port Read Timing Diagram ..........................................................................
13-13
13-15
Timer Inputs Timing Diagram .......................................................................
13-14
13-16
Output Compare Timing Diagram ................................................................
13-15
13-17
Input Capture Timing Diagram .....................................................................
13-15
13-18
Non-multiplexed Expanded Bus ...................................................................
13-18
13-19
SPI Master Timing (CPHA = 0) ....................................................................
13-20
SPI Master Timing (CPHA = 1) ....................................................................
13-20
13-21
SPI Slave Timing (CPHA = 0) ......................................................................
13-21
13-22
SPI Slave Timing (CPHA = 1) ......................................................................
13-21
13-23
Event Counter Mode 1, 2, 3 – Clock Input Timing Diagram .........................
13-22
13-24
Event Counter Mode 1, 2, 3 – Clock Gate Input Timing Diagram ................
13-23
A-1
MC68HC11G7 Functional Block Diagram ...................................................
A-1
A-2
MC68HC11G7 Memory Map .......................................................................
A-2
B-1
MC68HC711G5 Functional Block Diagram .................................................
B-1
B-2
MC68HC711G5 Memory Map .....................................................................
B-2
B-3
Block Diagram of MC68HC711G5 in PROG Mode ......................................
B-3
LIST OF ILLUSTRATIONS (Concluded)
Paragraph
Page
Number
Title
Number
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.