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參數(shù)資料
| 型號： | MC68HC11G7CFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 188/195頁 |
| 文件大?。?/td> | 1940K |
| 代理商： | MC68HC11G7CFN |
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SERIAL COMMUNICATIONS INTERFACE
7-2
Framing error detect.
Noise detect.
Overrun detect.
Receiver data register full flag.
7.1.3
SCI Transmitter Features
Transmit data register empty flag.
Transmit complete flag.
Send break.
7.2
FUNCTIONAL DESCRIPTION
A block diagram of the SCI is shown in Figure 7-1. The user has option bits in serial control register
1 (SCCR1) to select the “wake-up” method (WAKE bit) and data word length (M bit) of the SCI. Serial
communications control register 2 (SCCR2) provides control bits which individually enable/disable
the transmitter or receiver (TE and RE, respectively), enable system interrupts (TIE, TCIE, ILIE) and
provide the wake-up enable bit (RWU) and the send break code bit (SBK). Control bits in the baud
rate register (BAUD) allow the user to select one of 32 different baud rates for the transmitter and
receiver.
Data transmission is initiated by a write to the serial communications data register (SCDR). Provided
the transmitter is enabled, data stored in the SCDR is transferred to the transmit data shift register.
This transfer of data sets the transmit data register empty flag (TDRE) in the SCI status register
(SCSR) and may generate an interrupt if the transmit interrupt is enabled. The transfer of data to
the transmit data shift register is synchronized with the bit rate clock (Figure 7-2). All data is
transmitted least significant bit first. Upon completion of data transmission, the transmission
complete flag (TC) in the SCSR is set (provided no pending data, preamble or break is to be sent),
and an interrupt may be generated if the transmit complete interrupt is enabled. If the transmitter
is disabled, and the data, preamble or break (in the transmit data shift register) has been sent, the
TC bit will also be set. This will also generate an interrupt if the transmission complete interrupt
enable bit (TCIE) is set. If the transmitter is disabled in the middle of a transmission, that character
will be completed before the transmitter gives up control of the TXD pin.
When SCDR is read, it contains the last data byte received, provided that the receiver is enabled.
The receive data register full flag bit (RDRF) in the SCSR is set to indicate that a data byte has been
transferred from the input serial shift register to the SCDR, which can cause an interrupt if the
receiver interrupt is enabled. The data transfer from the input serial shift register to the SCDR is
synchronized by the receiver bit rate clock. The OR (overrun), NF (noise), or FE (framing) error flags
in the SCSR may be set if data reception errors occurred.
An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which detects
idle line transmission) in SCSR is set. This allows a receiver that is not in the wake-up mode to detect
the end of a message or the preamble of a new message, or to resychronize with the transmitter.
A valid character must be received before the idle line condition or the IDLE bit will not be set and
and idle line interrupt will not be generated.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| MC68HC11K0 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
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| MC68HC11K0CFN4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC11K0CFNE3 | 功能描述:8位微控制器 -MCU 8B MCU 768 RAM - EPP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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