參數(shù)資料
型號(hào): MC68HC11G7CFN
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84
封裝: PLASTIC, LCC-84
文件頁(yè)數(shù): 37/195頁(yè)
文件大小: 1940K
代理商: MC68HC11G7CFN
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EVENT COUNTER
11-1
SECTION 11
EVENT COUNTER
11.1
INTRODUCTION
The event counter consists of two distinct functional blocks. One block functions as an 8-bit pulse
accumulator unit (PA), the other as an 8-bit pulse width modulation unit (PWM). Each unit has its
own 8-bit counter and two 8-bit compare registers.
Four software selectable operating modes provide different configurations of the PA and PWM, their
interconnection and their combined operation. (The operating mode is selected using the event
counter mode select bits, EVMDA and EVMDB in the event counter lock register (EVCLK)). All four
modes provide programmable PWM period, duty cycle and polarity. Note that these PWM circuits
differ from the main PWM section in that these can be driven by an external signal. A simplified block
diagram of each mode is shown in Figure 11-1.
In mode 0, the PA unit can modify the PWM output by adding a programmable offset to the
input signal and by controlling the clearing of the PWM unit, thereby controlling the period of
the output signal.
In mode 1, the event counter operates as separate PWM and PA units. The two units are not
interconnected and operate completely independently of each other, providing standard
programmable PWM and PA functions.
In mode 2, the PA unit counts the PWM output signal periods, which may be of varying duration and
modulation.
In mode 3, the PA unit acts as a programmable 8-bit (1 – 256 clock) prescaler for the PWM unit.
The 8-bit counters in the PWM and PA units can be driven by an external clock or by a derivative
of the E-clock (E or scaled E), generated by the on-chip time-base counter. The clock source is
controlled by two input selectors (INPUT1 and INPUT2). Depending on the mode of operation
selected, the input selectors are used to determine the following:
1)
Clock source,
2)
Active edge of the external signal (which may be used as a clock),
3)
The gated input of the internal clock,
4)
Counter clear
One output selector is used to control the polarity of the PWM output signal.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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