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參數(shù)資料
| 型號(hào)： | MC68HC11G7CFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 70/195頁 |
| 文件大?。?/td> | 1940K |
| 代理商： | MC68HC11G7CFN |
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CPU, ADDRESSING MODES AND INSTRUCTION SET
12-11
the original value of the D accumulator is automatically preserved in the index register while
the pointer is being manipulated in the D accumulator. When pointer calculations are finished,
another exchange simultaneously updates the index register and restores the D accumulator to its
former value.
The transfers between an index register and the stack pointer deserve additional comment. The
stack pointer always points at the next free location on the stack as opposed to the last thing that
was pushed onto the stack. The usual reason for transferring the stack pointer value into an index
register is to allow indexed addressing access to information that was formerly pushed onto the
stack. In such cases, the address pointed-to by the stack pointer is of no value since nothing has
been stored at that location yet. This explains why the value in the stack pointer is incremented
during transfers to an index register. There is a corresponding decrement of a 16-bit value as it is
transferred from an index register to the stack pointer.
12.3.3
Condition Code Register Instructions
This group of instructions allows the programmer to manipulate bits in the condition code register.
Table 12-8. Condition Code Register Instructions
Function
Mnemonic
INH
Clear Carry Bi
CLC
X
Clear Interrupt Mask Bit
CLI
X
Clear Overflow Bit
CLV
X
Set Carry Bit
SEC
X
Set Interrupt Mask Bit
SEI
X
Set Overflow Bit
SEV
X
Transfer A to CCR
TAP
X
Transfer CCR to A
TPA
X
At first look, it may appear that there should be a set and a clear instruction for each of the 8 bits
in the condition code register while these instructions are present for only 3 of the 8 bits (C, I
and V). Upon closer consideration there are good reasons for not including the set and clear
instructions for the other five bits.
The stop disable (S) bit is an unusual case because this bit is intended to lock out the STOP
instruction for those who view it as an undesirable function in their application. Providing set and
clear instructions for this bit would make it easier to enable STOP when it was not wanted or disable
STOP when it was wanted. The TAP instruction provides a way to change S but cuts the chances
of an undesirable change to S in half because the value of the A accumulator at the time the TAP
instruction is executed determines whether or not S will actually change.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC11K0 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC11K0CFN2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-Bit Microcontroller |
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| MC68HC11K0CFN4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC11K0CFNE3 | 功能描述:8位微控制器 -MCU 8B MCU 768 RAM - EPP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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