參數(shù)資料
型號： MCIMX258CVM4
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA400
封裝： 17 X 17 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-400
文件頁數(shù)： 107/154頁
文件大?。?/td> 1498K
代理商： MCIMX258CVM4
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
56
Freescale Semiconductor
3.7.6
External Memory Interface (EMI) Timing
The EMI module includes the enhanced SDRAM/LPDDR memory controller (ESDCTL), NAND Flash
controller (NFC), and wireless external interface module (WEIM). The following subsections give timing
information for these submodules.
Table 43. CSPI Interface Timing Parameters
ID
Parameter Description
Symbol
Minimum
Maximum
Units
t1
CSPI master SCLK cycle time
tclko
60.2
—
ns
t2
CSPI master SCLK high time
tclkoH
22.65
—
ns
t3
CSPI master SCLK low time
tclkoL
22.47
—
ns
t1’
CSPI slave SCLK cycle time
tclki
60.2
—
ns
t2’
CSPI slave SCLK high time
tclkiH
30.1
—
ns
t3’
CSPI slave SCLK low time
tclkiL
30.1
—
ns
t4
CSPI SCLK transition time
tpr
1
1 The output SCLK transition time is tested with 25 pF drive.
2.6
8.5
ns
t5
SSn output pulse width
tWsso
2Tsclk
2 +T
wait
3
2 T
sclk = CSPI clock period
3 T
wait = Wait time, as specified in the sample period control register
——
t5’
SSn input pulse width
tWssi
Tper
4
4 T
per = CSPI reference baud rate clock period (PERCLK2)
——
t6
SSn output asserted to first SCLK edge (SS output setup
time)
tSsso
3Tsclk
——
t6’
SSn input asserted to first SCLK edge (SS input setup
time)
tSssi
Tper
——
t7
CSPI master: Last SCLK edge to SSn negated (SS
output hold time)
tHsso
2Tsclk
——
t7’
CSPI slave: Last SCLK edge to SSn negated (SS input
hold time)
tHssi
30
—
ns
t8
CSPI master: CSPI1_RDY low to SSn asserted
(CSPI1_RDY setup time)
tSrdy
2Tper
5Tper
—
t9
CSPI master: SSn negated to CSPI1_RDY low
tHrdy
0—
ns
t10
Output data setup time
tSdatao
(tclkoL or tclkoH or
tclkiL or tclkiH) –
Tipg
5
5 T
ipg = CSPI main clock IPG_CLOCK period
——
t11
Output data hold time
tHdatao
tclkoL or tclkoH or
tclkiL or tclkiH
——
t12
Input data setup time
tSdatai
Tipg + 0.5
—
ns
t13
Input data hold time
tHdatai
0—
ns
t14
Pause between data word
tpause
0—
ns
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