參數(shù)資料
型號： MCIMX258CVM4
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA400
封裝： 17 X 17 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-400
文件頁數(shù)： 94/154頁
文件大?。?/td> 1498K
代理商： MCIMX258CVM4
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
44
Freescale Semiconductor
Figure 10. Read Sequence Timing Diagram
3.7.2
ATA Timing Parameters
Table 35 shows parameters used to specify the ATA timing. These parameters depend on the
implementation of the ATA interface on silicon, the bus buffer used, the cable delay and cable skew.
Table 34. WR1 /RD Timing Parameters
ID
Parameter
Symbol
Min.
Typ.
Max.
Units
OW7
Write 1 / read low time
tLOW1
15
μs
OW8
Transmission time slot
tSLOT
60
117
120
μs
OW9
Release time
tRELEASE
15
—
45
μs
Table 35. Timing Parameters
Name
Description
Value/Contributing Factor
T
Bus clock period
Peripheral clock frequency
ti_ds
Set-up time ata_data to ata_iordy edge (UDMA-in only)
UDMA0
UDMA1
UDMA2,UDMA3
UDMA4
UDMA5
15 ns
10 ns
7ns
5ns
4ns
ti_dh
Hold time ata_iordy edge to ata_data (UDMA-in only)
UDMA0,UDMA1,UDMA2,UDMA3,UDMA4
UDMA5
5.0 ns
4.6 ns
tco
Propagation delay bus clock L-to-H to
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data, ata_buffer_en
12.0 ns
tsu
Set-up time ata_data to bus clock L-to-H
8.5 ns
tsui
Set-up time ata_iordy to bus clock H-to-L
8.5 ns
thi
Hold time ata_iordy to bus clock H-to-L
2.5 ns
tskew1
Maximum difference in propagation delay bus clock L-to-H to any of the
following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow,
ata_dmack, ata_data (write), ata_buffer_en
7ns
OW7
OW8
OW9
1-Wire bus
(OWIRE_LINE)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MCIMX25LPDKJ 制造商:Freescale Semiconductor 功能描述:; LEADED PROCESS COMPATIBLE:YES; PEAK RE
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MCIMX25WPDK 功能描述:開發(fā)板和工具包 - ARM MCIMX25 PDK ForLINUX RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V
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