參數(shù)資料
型號: MCIMX258CVM4
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA400
封裝: 17 X 17 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-400
文件頁數(shù): 90/154頁
文件大小: 1498K
代理商: MCIMX258CVM4
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
40
Freescale Semiconductor
Note:
1. Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 3.0 V, and 105 °C. Minimum condition for tpr, tpo, and tpv:
bcs model, 1.3 V, I/O 3.6 V and –40 °C. Input transition time from core is 1 ns (20%–80%).
2. Minimum condition for tps: wcs model, 1.1 V, I/O 3.0 V, and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
3. Maximum condition for tdit: bcs model, 1.3 V, I/O 3.6 V, and –40 °C.
4. Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 3.0 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V,
I/O 3.6 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).
3.6.3.3
DDR_TYPE = 10 Max Setting I/O AC Parameters and Requirements
Table 29 shows AC parameters for DDR2 I/O.
Output pad dI/dt (max. drive)
tdit
25 pF
50 pF
89
95
202
213
435
456
mA/ns
3
Output pad dI/dt (high drive)
tdit
25 pF
50 pF
60
63
135
142
288
302
mA/ns
Output pad dI/dt (standard drive)
tdit
25 pF
50 pF
29
31
67
70
144
150
mA/ns
Input pad transition times
trfi
1.0 pF
0.07/0.08
0.11/0.12
0.16/0.20
ns
4
Input pad propagation delay, 50%–50%
tpi
1.0 pF
0.56/0.69
0.87/1.08
1.37/1.62
ns
Input pad propagation delay, 40%–60%
tpi
1.38/1.51
1.68/1.89
2.18/2.42
Table 29. AC Parameters for DDR2 I/O
Parameter
Symbol
Load
Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units
Notes
Duty cycle
Fduty
40
50
60
%
Clock frequency
f
133
MHz
Output pad transition times
tpr
25 pF
50 pF
0.53/0.52
1.01/0.98
0.80/0.72
1.49/1.34
1.19/1.04
2.21/1.90
ns
1
Output pad propagation delay, 50%–50%
tpo
25 pF
50 pF
0.93/1.25
1.26/1.54
1.56/1.70
2.07/2.19
2.52/2.53
3.29/3.24
ns
1
Output pad propagation delay, 40%–60%
tpo
25 pF
50 pF
1.01/1.17
1.27/1.53
1.60/1.75
2.00/2.14
2.49/2.52
3.11/3.10
ns
1
Output enable to output valid delay,
50%–50%
tpv
25 pF
50 pF
1.30/1.19
1.62/1.54
2.17/1.81
2.56/2.29
3.35/2.84
3.35/2.54
ns
1
Output enable to output valid delay,
40%–60%
tpv
25 pF
50 pF
1.39/1.27
1.64/1.55
2.13/1.86
2.62/2.23
3.38/2.83
4.14/2.38
ns
1
Output pad slew rate
tps
25 pF
50 pF
0.86/0.98
0.46/054
1.35/1.5
0.72/0.81
2.15/2.19
1.12/1.16
V/ns
2
Table 28. AC Parameters for SDRAM pbijtov18_33_ddr_clk I/O (continued)
Parameter
Symbol
Load
Condition
Min.
Rise/Fall
Typ.
Max.
Rise/Fall
Units
Notes
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