參數(shù)資料
型號: MCIMX258CVM4
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA400
封裝: 17 X 17 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-400
文件頁數(shù): 92/154頁
文件大?。?/td> 1498K
代理商: MCIMX258CVM4
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
42
Freescale Semiconductor
2. Minimum condition for tps: wcs model, 1.1 V, I/O 1.7 V, and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
3. Maximum condition for tdit: bcs model, 1.3 V, I/O 1.9 V, and –40 °C.
4. Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.7 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V,
I/O 1.9 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).
Table 31 shows the AC requirements for DDR2 I/O.
3.7
Module Timing and Electrical Parameters
This section contains the timing and electrical parameters for i.MX25 modules.
3.7.1
1-Wire Timing Parameters
Figure 7 shows the reset and presence pulses (RPP) timing for 1-Wire.
Figure 7. 1-Wire RPP Timing Diagram
Table 31. AC Requirements for DDR2 I/O
Parameter1
1 Note that the Jedec SSTL_18 specification (JESD8-15a) for an SSTL interface for class II operation supersedes any
specification in this document.
Symbol
Min.
Max.
Units
AC input logic high
VIH(ac)
OVDD/2 + 0.25
OVDD + 0.3
V
AC input logic low
VIL(ac)
–0.3
OVDD/2 – 0.25
V
AC differential input voltage2
2 Vid(ac) specifies the input differential voltage |Vtr–Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The minimum value is equal to Vih(ac)–Vil(ac)
Vid(ac)
0.5
OVDD + 0.6
V
AC differential cross point voltage for input3
3 The typical value of Vix(ac) is expected to be about 0.5
× OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
Vix(ac)
OVDD/2–0.175
OVDD/2 + 0.175
V
AC differential cross point voltage for output4
4 The typical value of Vox(ac) is expected to be about 0.5
× OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac)
indicates the voltage at which differential output signal must cross. Cload = 25 pF.
Vox(ac)
OVDD/2–0.125
OVDD/2 + 0.125
V
1-Wire bus
1-Wire Memory Device
“Presence Pulse”
(OWIRE_LINE)
1-Wire Tx
“Reset Pulse”
OW1
OW2
OW3
OW4
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