參數(shù)資料
型號(hào): MCIMX258CVM4
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA400
封裝: 17 X 17 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-400
文件頁數(shù): 29/154頁
文件大?。?/td> 1498K
代理商: MCIMX258CVM4
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
124
Freescale Semiconductor
3.7.20.2
USB Parallel Interface Timing
Table 98 defines the USB parallel interface signals.
Figure 97 shows the USB parallel mode transmit/receive waveform. Table 99 describes the timing
parameters (USB15–USB17) shown in the figure.
Figure 97. USB Parallel Mode Transmit/Receive Waveform
4
Package Information and Contact Assignment
4.1
400 MAPBGA—Case 17x17 mm, 0.8 mm Pitch
Figure 98 shows the 17
×17 mm i.MX25 production package. The following notes apply to Figure 98:
All dimensions in millimeters.
Dimensioning and tolerancing per ASME Y14.5M-1994.
Table 98. Signal Definitions for USB Parallel Interface
Name
Direction
Signal Description
USB_Clk
In
Interface clock—All interface signals are synchronous to USB_Clk
USB_Data[7:0]
I/O
Bidirectional data bus, driven low by the link during idle—Bus ownership is determined by the
direction
USB_Dir
In
Direction—Control the direction of the data bus
USB_Stp
Out
Stop—The link asserts this signal for one clock cycle to stop the data stream currently on the bus
USB_Nxt
In
Next—The PHY asserts this signal to throttle the data
Table 99. USB Timing Specification in Parallel Mode
ID
Parameter
Min.
Max.
Unit
Conditions/
Reference Signal
US15
Setup time (Dir&Nxt in, Data in)
6.0
ns
10 pF
US16
Hold time (Dir&Nxt in, Data in)
0.0
ns
10 pF
US17
Output delay time (Stp out, Data out
9.0
ns
10 pF
USB_Dir/Nxt
USB_Stp
US17
US16
USB_Data
US15
US16
US15
US17
USB_Clk
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