參數(shù)資料
型號: MCIMX31
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應用處理器
文件頁數(shù): 20/170頁
文件大?。?/td> 1562K
代理商: MCIMX31
i.MX31/i.MX31L Advance Information, Rev. 1.4
20
Freescale Semiconductor
Preliminary
Functional Description and Application Information
includes support for setting breakpoints, Single-Step & Trace and register dump capability. In addition, all
memory locations are accessible from the debug port.
2.3.27
Subscriber Identification Module (SIM)
The SIM Interface Module (SIM) is designed to facilitate communication to SIM cards or Eurochip
pre-paid phone cards. The SIM module has two ports that can be used to interface with the various cards.
The interface with the MCU is via a 16-bit connection, The SIM module I/O interface can be operated in
one of three modes of operation.
Two wire interface.
In this mode both the IC pin RX and IC pin TX are used to interface to the smartcard.
This is activated by resetting the 3volt bit in the port control register to a “0”.
External one wire interface
. In this mode the IC pins RX and TX are tied together external to the IC and
routed to the smartcard. The 3volt bit in the port control register is reset to a “0” and the OD bit in the
OD_CONFIG register is set to a “1”. For this interface to work properly the IC pin (RX-TX) must be pulled
high by a resistor. The value should be selected small enough to give a fast enough rise time.
Internal one wire interface.
In this mode the IC pin TX is routed to the smartcard. The receive pin RX is
connected to the TX pin internal to the IC. The 3volt bit in the port control register is reset to a “1” and the
OD bit in the OD_CONFIG register is set to a “1”. For this interface to work properly the IC pin TX must
be pulled high by a resistor. The value should be selected small enough to give a fast enough rise time.
2.3.28
Secure JTAG Controller (SJC)
The IEEE1149.1 JTAG test access port (TAP) supports IEEE1149.1 v2001 standard features, access to
OnCE and ICE of each Core, debug features to improve controllability and absorbability of the Cores for
debug purposes, manufacturing test features (special test modes, PLL bypass, memory BIST and
Burn-in...). The SJC provides debug and test control with the maximum security and provide a flexible
architecture for future derivatives or future multi-cores architecture (how to add-remove a Core, software
and hardware implications). JTAG pins can be muxed to the PCS bus connectors.
The SJC operates at maximum 1/8 the slowest frequency of the accessed OnCE/ICE. For example in
normal operation (no core in low-power mode), this frequency will be 1/8 of the SDMA frequency if this
core is present in the TDI-TDO chain (serially connected with other cores or standalone). User needs also
to take into account the 25MHz frequency limitation on the CE bus.
In addition, secure JTAG options are provided to protect debug resources from attacks by unauthorized
users. The secure JTAG design prevents the debug architecture from compromising security.
2.3.29
Synchronous Serial Interface (SSI)
The SSI is a full-duplex, serial port that allows the chip to communicate with a variety of serial devices.
These serial devices can be standard codecs, Digital Signal Processors (DSPs), microprocessors,
peripherals, and popular industry audio codecs that implement the inter-IC sound bus standard (I2S) and
Intel AC97 standard.
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相關代理商/技術參數(shù)
參數(shù)描述
MCIMX31_07 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Multimedia Applications Processors
MCIMX31_08 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Multimedia Applications Processors
MCIMX31_09 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Multimedia Applications Processors
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