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參數(shù)資料
| 型號(hào)： | MCIMX31 |
| 廠(chǎng)商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Multimedia Applications Processors |
| 中文描述： | 多媒體應(yīng)用處理器 |
| 文件頁(yè)數(shù)： | 72/170頁(yè) |
| 文件大?。?/td> | 1562K |
| 代理商： | MCIMX31 |
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i.MX31/i.MX31L Advance Information, Rev. 1.4
72
Freescale Semiconductor
Preliminary
Electrical Characteristics
4.3.5
ATA Electrical Specifications (ATA Bus, Bus Buffers)
This section discusses ATA electricals and explains how to make sure the ATA interface meets timing. To
meet electrical spec on the ATA bus, several requirements must be met. For a detailed description, refer
to the ATA specification.
This electrical spec must be met for the pads used on the ATA I/Os if no bus buffers and bus transceivers
are used.
Alternative is to use bus buffers. This is the only way to operate the ATA interface if 3.3 Volt or 5.0 Volt
compatibility on the ATA bus is wanted, and no 3.3 Volt or 5.0 Volt tolerant pads on the device are
available.
The use of bus buffers introduces delay on the bus and introduces skew between signal lines. These factors
make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast
UDMA mode operation is needed, this may not be compatible with bus buffers.
Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.
According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with
a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.
When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a
direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus
should drive from host to device. When its low, the bus should drive from device to host. Steering of the
signal is such that contention on the host and device tri-state busses is always avoided.
4.3.5.1
Timing Parameters
In the timing equations, some timing parameters are used. These parameters depend on the implementation
of the ATA interface on silicon, the bus buffer used, the cable delay and cable skew.
Table 23
shows ATA
timing parameters.
Table 23. ATA Timing Parameters
Name
Description
Value/
Contributing Factor
1
T
Bus clock period (ipg_clk_ata)
peripheral clock
frequency
ti_ds
Set-up time
ata_data
to
ata_iordy
edge (UDMA-in only)
11 ns
ti_dh
hold time
ata_iordy
edge to
ata_data
(UDMA-in only)
6 ns
tco
propagation delay bus clock L-to-H to
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data, ata_buffer_en
15 ns
tsu
set-up time
ata_data
to bus clock L-to-H
19 ns
tsui
set-up time
ata_iordy
to bus clock H-to-L
9 ns
thi
hold time
ata_iordy
to bus clock H to L
5 ns
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相關(guān)代理商/技術(shù)參數(shù) |
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| MCIMX31_07 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Multimedia Applications Processors |
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