
Signal Descriptions
i.MX31/i.MX31L Advance Information, Rev. 1.4
Freescale Semiconductor
31
Preliminary
SCK6
AudioPort
6-BT
(PP3)
Tx Serial Clock
ATA_DATA13
–
sw_mux_ctl_
sck6[6:0]
–
–
IPU_DI
AGB[16]
TRACE
DATA_
13
EVNTB
US_14
M3IF_C
HOSEN
_MAST
ER_1
MCU1_
25
SFS6
AudioPort
6-BT
(PP3)
Tx Frame Sync
USBH1_SUS
PEND
–
sw_mux_ctl_
sfs6[6:0]
–
–
IPU_DI
AGB[17]
TRACE
DATA_
14
EVNTB
US_15
M3IF_C
HOSEN
_MAST
ER_2
MCU1_
26
CSPI1_MOSI
CSPI1_
BB
Master Out/Slave In.
ATA_DATA0
ATA_IN
TRQ
sw_mux_ctl_
cspi1_mosi[6
:0]
USBH1
_RXDM
RXD3
IPU_DI
AGB[18]
TRACE
DATA_
15
–
–
–
CSPI1_MISO
CSPI1_
BB
Slave In/Master Out.
ATA_DATA1
ATA_BU
FFER_E
N
sw_mux_ctl_
cspi1_miso[6
:0]
USBH1
_RXDP
TXD3
IPU_DI
AGB[19]
TRACE
DATA_
16
–
–
–
CSPI1_SS0
CSPI1_
BB
Slave Select (Selectable
polarity).
ATA_DATA2
ATA_DM
ARQ
sw_mux_ctl_
cspi1_ss0[6:
0]
USBH1
_TXDM
CSPI3_
SS2
IPU_DI
AGB[20]
TRACE
DATA_
17
–
–
–
CSPI1_SS1
CSPI1_
BB
Slave Select (Selectable
polarity).
ATA_DATA3
ATA_DA
0
sw_mux_ctl_
cspi1_ss1[6:
0]
USBH1
_TXDP
CSPI2_
SS3
IPU_DI
AGB[21]
TRACE
DATA_
18
–
–
–
CSPI1_SS2
CSPI1_
BB
Slave Select (Selectable
polarity).
ATA_DATA4
ATA_DA
1
sw_mux_ctl_
cspi1_ss2[6:
0]
USBH1
_RCV
CSPI3_
SS3
IPU_DI
AGB[22]
TRACE
DATA_
19
–
–
–
CSPI1_SCLK
CSPI1_
BB
Serial Clock.
ATA_DATA5
ATA_DA
2
sw_mux_ctl_
cspi1_sclk[6:
0]
USBH1
_OEB
RTS3
IPU_DI
AGB[23]
–
–
–
–
CSPI1_SPI_
RDY
CSPI1_
BB
Serial Data Ready.
ATA_DATA6
–
sw_mux_ctl_
cspi1_spi_rd
y[6:0]
USBH1
_FS
CTS3
IPU_DI
AGB[24]
–
–
–
–
CSPI2_MOSI
CSPI2_
PM
Master Out/Slave In.
–
–
sw_mux_ctl_
cspi2_mosi
[6:0]
I2C2_S
CL
–
–
–
–
–
–
CSPI2_MISO
CSPI2_
PM
Slave In/Master Out.
–
–
sw_mux_ctl_
cspi2_miso
[6:0]
I2C2_S
DA
–
–
–
–
–
–
CSPI2_SS0
CSPI2_
PM
Slave Select (Selectable
polarity).
–
–
sw_mux_ctl_
cspi2_ss0
[6:0]
CSPI3_
SS0
–
–
–
–
–
–
CSPI2_SS1
CSPI2_
PM
Slave Select (Selectable
polarity).
–
–
sw_mux_ctl_
cspi2_ss1
[6:0]
CSPI3_
SS1
CSPI1_
SS3
–
–
–
–
–
CSPI2_SS2
CSPI2_
PM
Slave Select (Selectable
polarity).
–
–
sw_mux_ctl_
cspi2_ss2
[6:0]
I2C3_S
DA
IPU_FL
ASH_S
TROBE
–
–
–
–
–
CSPI2_SCLK
CSPI2_
PM
Serial Clock.
–
–
sw_mux_ctl_
cspi2_sclk
[6:0]
I2C3_S
CL
–
–
–
–
–
–
CSPI2_SPI_
RDY
CSPI2_
PM
–
–
–
sw_mux_ctl_
cspi2_spi_
rdy[6:0]
–
–
–
–
–
–
–
RXD1
UART1_
GPS
Rx Data. (+CE Bus 12)
TRSTB
–
sw_mux_ctl_
rxd1[6:0]
USBOT
G_DATA
4
PP4_TX
DAT/
STDA
–
DSR_
DCE1
–
–
MCU2_
4
TXD1
UART1_
GPS
Tx Data. + (CE Bus 10)
TCK
–
sw_mux_ctl_
txd1[6:0]
USBOT
G_DATA
1
PP4_TX
CLK/
SCK
–
RI_DCE
1
–
–
MCU2_
5
RTS1
UART1_
GPS
Request to send. + (CE
Bus 9)
–
–
sw_mux_ctl_
rts1[6:0]
–
PP4_TX
FS/FS
–
DCD_D
CE1
–
–
MCU2_
6
CTS1
UART1_
GPS
Clear to send. + CE Bus 8)
DE
–
sw_mux_ctl_
cts1[6:0]
–
–
–
–
–
–
MCU2_
7
Table 4. Functional Multiplexing (continued)
Pin Name
Group
Description
Hardware
Mode 1
HW
Mode
2
SW_
MUX_
EN
Alt
Mode
1
Alt
Mode
2
Alt
Mode
3
Alt
Mode
4
Alt
Mode
5
Alt
Mode
6
GPIO