參數(shù)資料
型號(hào): MCIMX31
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應(yīng)用處理器
文件頁數(shù): 90/170頁
文件大小: 1562K
代理商: MCIMX31
i.MX31/i.MX31L Advance Information, Rev. 1.4
90
Freescale Semiconductor
Preliminary
Electrical Characteristics
NOTE
High is defined as 80% of signal value and low is defined as 20% of signal value.
WE4
Clock rise/fall to CS[x] invalid
–3
3
ns
WE5
Clock rise/fall to RW Valid
–3
3
ns
WE6
Clock rise/fall to RW Invalid
–3
3
ns
WE7
Clock rise/fall to OE Valid
–3
3
ns
WE8
Clock rise/fall to OE Invalid
–3
3
ns
WE9
Clock rise/fall to EB[x] Valid
–3
3
ns
WE10
Clock rise/fall to EB[x] Invalid
–3
3
ns
WE11
Clock rise/fall to LBA Valid
–3
3
ns
WE12
Clock rise/fall to LBA Invalid
–3
3
ns
WE13
Clock rise/fall to Output Data Valid
–3.5
10
ns
WE14
Clock rise to Output Data Invalid
–3.5
10
ns
WE15
Input Data Valid to Clock rise, FCE=0
–2
10
ns
WE16
Cloc/k rise to Input Data Invalid, FCE=0
–7
0
ns
WE15
Input Data Valid to Clock rise, FCE=1
–2
10
ns
WE16
Clock rise to Input Data Invalid, FCE=1
–7
0
ns
WE17
ECB setup time, FCE=0
–2
10
ns
WE18
ECB hold time, FCE=0
–7
0
ns
WE17
ECB setup time, FCE=1
–2
10
ns
WE18
ECB hold time, FCE=1
–7
0
ns
WE19
DTACK setup time
1
ns
WE20
DTACK hold time
0
4
ns
WE20
DTACK hold time (Level sensitive mode, EW=1
implies wsc < 111111)
6
12
ns
WE21
BCLK High Level Width
2, 3
Tcycle/
2-3
ns
WE22
BCLK Low Level Width
2, 3
Tcycle/
2-3
ns
WE23
BCLK Cycle time
2
1
Not required.
2
BCLK parameters are being measured from the 50% VDD.
3
The actual cycle time is derived from the AHB bus clock frequency.
Table 33. WEIM Bus Timing Parameters (continued)
ID
Parameter
1.8 V
Unit
Min
Max
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