參數(shù)資料
型號: MCIMX31
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應用處理器
文件頁數(shù): 62/170頁
文件大?。?/td> 1562K
代理商: MCIMX31
i.MX31/i.MX31L Advance Information, Rev. 1.4
62
Freescale Semiconductor
Preliminary
Electrical Characteristics
Table 10
gives details of the applied voltages to the i.MX31/i.MX31L Core Supply I/O versus the
frequencies of the ARM11 core.
Table 11
provides information for interface frequency limits. For more details about clocks characteristics,
see
Section 4.3.8, “DPLL Electrical Specifications
on page 82
.
Table 12
provides the DC absolute maximum operating conditions.
CAUTION
Stresses beyond those listed under
“DC Absolute Maximum Operating
Conditions,”
(
Table 12
) may cause permanent damage to the device. These
are stress ratings only. Functional operation of the device at these or any
other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability.
6
Recommended maximum OVDD operating voltage is 3.1 V for GPIO in either slow or fast mode. Switching duty cycles must
be limited to a cumulative duration of 1 year or less (20% duty cycle for a 5yr rated part) to sustain a MAX OVDD operating
voltage of 3.3V without significant device degradation. A switching cycle is defined as the period of time that the pad is powered
to OVDD and actively switching. Switching cycles exceeding this limit may affect device performance or cause permanent
damage to the device.
7
The performance at 1.8 V of GPIO devices that are operated at 3.3 V over an extended period of time (for example. 2 years or
longer at a 20% duty cycle) is not guaranteed. Reliability degradation may render the device too slow or inoperable.
8
Overshoot and undershoot conditions (transitions above OVDD and below OVSS) on switching pads must be held below 0.6 V,
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be
controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods.
Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
9
For normal operating conditions, PLLs’ and core supplies must maintain the following relation: PLL
Core – 100 mV. In other
words, for a 1.6 V core supply, PLL supplies must be set to 1.5 V or higher.
10
Providing a voltage that is lower than specified does not prevent the fuses from being blown if attempting to program a fuse.
Table 10. Voltage versus Core Frequency
ID
Core
Symbol
Min (V)
Max (V)
Frequency (MHz)
1
ARM11 (V
DD
)
f
ARM
1.22
1
1
As measured at the ball. Recommended settings for PMIC (Power Management IC) is 1.275 V.
2
All overdrive/25% duty-cycles restrictions apply, as specified in
Table 9
.
3
As measured at the ball. Recommended voltage settings for PMIC is 1.6 V.
1.65
1, 2
0–400
2
f
ARM
1.55
3
1.65
3
401–532
Table 11. Interface Frequency
ID
Parameter
Symbol
Min
Typ
Max
Units
1
JTAG TCK Frequency
f
JTAG
DC
5
10
MHz
2
CKIL Frequency
f
CKIL
32
32.768
38.4
kHz
3
CKIH Frequency
f
CKIH
10
26
100
MHz
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