參數(shù)資料
型號(hào)： MCIMX514AJM6C
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529
封裝： 19 X 19 MM, 0.8 MM PITCH, ROHS COMPLIANT, BGA-529
文件頁數(shù)： 114/172頁
文件大?。?/td> 2218K
代理商： MCIMX514AJM6C
i.MX51A Automotive and Infotainment Applications Processors, Rev. 4
46
Freescale Semiconductor
Electrical Characteristics
4.6.5
DPLL Electrical Parameters
Table 48 shows the DPLL electical parameters.
4.6.6
NAND Flash Controller (NFC) Parameters
This section provides the relative timing requirements among different signals of NFC at the module level
in the different operational modes.
Timing parameters in Figure 14, through Figure 17, Figure 19, and Table 50 show the default NFC mode
(asymmetric mode) using two Flash clock cycles per one access of RE_B and WE_B.
Timing parameters in Figure 14, Figure 15, Figure 16, Figure 18, Figure 19, and Table 50 show symmetric
NFC mode using one Flash clock cycle per one access of RE_B and WE_B.
Table 48. DPLL Electrical Parameters
Parameter
Test Conditions/Remarks
Min
Typ
Max
Unit
Reference clock frequency range1
1 Device input range cannot exceed the electrical specifications of the CAMP, see Table 47.
—
10
—
100
MHz
Reference clock frequency range after
pre-divider
—10
—
40
MHz
Output clock frequency range (dpdck_2)
—
300
—
1025
MHz
Pre-division factor2
2 The values specified here are internal to DPLL. Inside the DPLL, a “1” is added to the value specified by the user.Therefore,
the user has to enter a value “1” less than the desired value at the inputs of DPLL for PDF and MFD.
—1
—
16
—
Multiplication factor integer part
—
5
—
15
—
Multiplication factor numerator3
3 The maximum total multiplication factor (MFI + MFN/MFD) allowed is 15.Therefore, if the MFI value is 15, MFN value must be
zero.
Should be less than denominator
–67108862
—
67108862
—
Multiplication factor denominator2
—
1
—
67108863
—
Output Duty Cycle
—
48.5
50
51.5
%
Frequency lock time4
(FOL mode or non-integer MF)
4 T
dpdref is the time period of the reference clock after predivider.According to the specification, the maximum lock time in FOL
mode is 398 cycles of divided reference clock when DPLL starts after full reset.
——
—
398
Tdpdref
Phase lock time
—
100
s
Frequency jitter5 (peak value)
5 Tdck is the time period of the output clock, dpdck_2.
—
0.02
0.04
Tdck
Phase jitter (peak value)
FPL mode, integer and fractional MF
—
2.0
3.5
ns
Power dissipation
fdck = 300 MHz @ avdd = 1.8 V,
dvdd = 1.2 V
fdck = 650 MHz @ avdd = 1.8 V,
dvdd = 1.2 V
—
0.65 (avdd)
0.92 (dvdd)
1.98 (avdd)
1.8 (dvdd)
mW
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MCIMX514AJM6CR2 制造商:Freescale Semiconductor 功能描述:ELVIS 3.0 AUTO - Tape and Reel
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MCIMX515DJM8C 制造商:Freescale Semiconductor 功能描述:; LEADED PROCESS COMPATIBLE:YES; PEAK RE
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