參數(shù)資料
型號(hào): MCIMX514AJM6C
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529
封裝: 19 X 19 MM, 0.8 MM PITCH, ROHS COMPLIANT, BGA-529
文件頁數(shù): 149/172頁
文件大?。?/td> 2218K
代理商: MCIMX514AJM6C
i.MX51A Automotive and Infotainment Applications Processors, Rev. 4
78
Freescale Semiconductor
Electrical Characteristics
4.7.6.1
Standard and Fast Mode Timing Parameters
Figure 46 depicts the standard and fast mode timings of HS-I2C module, and Table 75 lists the timing
characteristics.
Figure 46. HS-I2C Standard and Fast Mode Bus Timing
Table 75. HS-I2C Timing Parameters—Standard and Fast Mode
ID
Parameter
Standard Mode
Fast Mode
Unit
Min
Max
Min
Max
IC1
SCLH cycle time
10
2.5
s
IC2
Hold time (repeated) START condition
4.0
0.6
s
IC3
Set-up time for STOP condition
4.0
0.6
s
IC4
Data hold time
01
1 A device must internally provide a hold time of at least 300 ns for SDAH signal in order to bridge the undefined region of the
falling edge of SCLH.
3.452
2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC6) of the SCLH signal
0.92
s
IC5
HIGH Period of SCLH Clock
4.0
0.6
s
IC6
LOW Period of the SCLH Clock
4.7
1.3
s
IC7
Set-up time for a repeated START condition
4.7
0.6
s
IC8
Data set-up time
250
1003
3 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC8)
of 250 ns must then be met. This automatically is the case if the device does not stretch the LOW period of the SCLH signal.
If such a device does stretch the LOW period of the SCLH signal, it must output the next data bit to the SDAH line max_rise_time
(ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)
before the SCLH line is released.
—ns
IC9
Bus free time between a STOP and START condition
4.7
1.3
s
IC10
Rise time of both SDAH and SCLH signals
1000
20+0.1Cb
4
4 C
b = total capacitance of one bus line in pF.
300
ns
IC11
Fall time of both SDAH and SCLH signals
300
20+0.1Cb
300
ns
IC12
Capacitive load for each bus line (Cb)
100
100
pF
IC10
IC11
IC9
IC2
IC8
IC4
IC7
IC3
IC6
IC10
IC5
IC11
START
STOP
START
SDAH
SCLH
IC1
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