參數(shù)資料
型號： MCIMX514AJM6C
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529
封裝： 19 X 19 MM, 0.8 MM PITCH, ROHS COMPLIANT, BGA-529
文件頁數(shù)： 159/172頁
文件大小： 2218K
代理商： MCIMX514AJM6C
Electrical Characteristics
i.MX51A Automotive and Infotainment Applications Processors, Rev. 4
Freescale Semiconductor
87
VSYNC—Vertical synchronization
DRDY—Active data
All synchronous display controls are generated on base of an internal generated “l(fā)ocal start point”. The
synchronous display controls can be placed on time axis with DI’s offset, up and down parameters. The
display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved relative
to the local start point.
4.7.8.5.2
LCD Interface Functional Description
Figure 52 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure
signals are shown with negative polarity. The sequence of events for active matrix interface timing is:
DI_CLK internal DI clock, used for calculation of other controls.
IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is
selected). In active mode, IPP_DISP_CLK runs continuously.
HSYNC causes the panel to start a new line. (Usually IPP_PIN_2 is used as HSYNC)
VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
(Usually IPP_PIN_3 is used as VSYNC)
DRDY acts like an output enable signal to the CRT display. This output enables the data to be
shifted onto the display. When disabled, the data is invalid and the trace is off.
(For DRDY can be used either synchronous or asynchronous generic purpose pin as well.)
Figure 52. Interface Timing Diagram for TFT (Active Matrix) Panels
4.7.8.5.3
TFT Panel Sync Pulse Timing Diagrams
Figure 53 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
the data. All shown on the figure parameters are programmable. All controls are started by corresponding
123
m
m-1
HSYNC
VSYNC
HSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n-1
LINE n
DRDY
IPP_DISP_CLK
IPP_DATA
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCIMX514AJM6CR2 制造商:Freescale Semiconductor 功能描述:ELVIS 3.0 AUTO - Tape and Reel
MCIMX515CJM6C 功能描述:處理器 - 專門應(yīng)用 iMX515 App Processor RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX515CJM6CR2 功能描述:處理器 - 專門應(yīng)用 i.MX51 32bit 800 MHz RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX515DJM8C 功能描述:處理器 - 專門應(yīng)用 iMX515 App Processor Extended Temp RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX515DJM8C 制造商:Freescale Semiconductor 功能描述:; LEADED PROCESS COMPATIBLE:YES; PEAK RE
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