參數(shù)資料
型號: MCIMX514AJM6C
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529
封裝: 19 X 19 MM, 0.8 MM PITCH, ROHS COMPLIANT, BGA-529
文件頁數(shù): 165/172頁
文件大?。?/td> 2218K
代理商: MCIMX514AJM6C
i.MX51A Automotive and Infotainment Applications Processors, Rev. 4
92
Freescale Semiconductor
Electrical Characteristics
4.7.8.6
Interface to a TV Encoder
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The timing of
the interface is described in Figure 56.
NOTE
The frequency of the clock DISP_CLK is 27 MHz (within 10%)
The HSYNC, VSYNC signals are active low.
The DRDY signal is shown as active high.
The transition to the next row is marked by the negative edge of the
HSYNC signal. It remains low for a single clock cycle
The transition to the next field/frame is marked by the negative edge of
the VSYNC signal. It remains low for at least one clock cycles
At a transition to an odd field (of the next frame), the negative edges
of VSYNC and HSYNC coincide.
At a transition is to an even field (of the same frame), they do not
coincide.
The active intervals—during which data is transferred—are marked by
the HSYNC signal being high.
2 Display interface clock down time
3 Display interface clock up time
where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
Tdicd
1
2
---T
diclk
ceil
×
2
DISP_CLK_DOWN
×
DI_CLK_PERIOD
-------------------------------------------------------------
=
Tdicu
1
2
---T
diclk
ceil
×
2
DISP_CLK_UP
×
DI_CLK_PERIOD
---------------------------------------------------
=
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCIMX514AJM6CR2 制造商:Freescale Semiconductor 功能描述:ELVIS 3.0 AUTO - Tape and Reel
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MCIMX515DJM8C 制造商:Freescale Semiconductor 功能描述:; LEADED PROCESS COMPATIBLE:YES; PEAK RE