參數(shù)資料
型號(hào)： MCIMX514AJM6C
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529
封裝： 19 X 19 MM, 0.8 MM PITCH, ROHS COMPLIANT, BGA-529
文件頁數(shù)： 115/172頁
文件大?。?/td> 2218K
代理商： MCIMX514AJM6C
Electrical Characteristics
i.MX51A Automotive and Infotainment Applications Processors, Rev. 4
Freescale Semiconductor
47
With reference to the timing diagrams, a high is defined as 80% of signal value and low is defined as 20%
of signal value. All parameters are given in nanoseconds. The BGA contact load used in calculations is 20
pF (except for NF16 - 40 pF) and there is max drive strength on all contacts.
All timing parameters are a function of T, which is the period of the flash_clk clock (“enfc_clk” at system
level). This clock frequency can be controlled by the user, configuring CCM (SoC clock controller). The
clock is derived from emi_slow_clk after single divider. Table 49 demonstrates few examples for clock
frequency settings.
NOTE
A potential limitation for minimum clock frequency may exist for some
devices. When the clock frequency is too low the actual data bus capturing
might occur after the specified trhoh (RE_B high to output hold) period.
Setting the clock frequency above 25.6 MHz (T = 39 ns) guarantees proper
operation for devices having trhoh > 15 ns. It is also recommended to set the
NFC_FREQ_SEL Fuse accordingly to initiate the boot with 33.33 MHz
clock.
Lower frequency operation can be supported for most available devices in
the market, relying on data lines Bus-Keeper logic. This depends on device
behavior on the data bus in the time interval between data output valid to
data output high-Z state. In NAND device parameters this period is marked
between trhoh and trhz (RE_B high to output high-Z). In most devices, the
data transition from valid value to high-Z occurs without going through
other states. Setting the data bus pads to Bus-Keeper mode in the IOMUX
registers, keeps the data bus valid internally after the specified hold time,
allowing proper capturing with slower clock.
Table 49. NFC Clock Settings Examples
emi_slow_clk (MHz)
nfc_podf (Division Factor)
enfc_clk (MHz)
T—Clock Period (ns)1
1 Rounded up to whole nanoseconds.
133 (max value)
5 (reset value)
26.6
38
133
4
33.25
31
133
3
44.33
23
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCIMX514AJM6CR2 制造商:Freescale Semiconductor 功能描述:ELVIS 3.0 AUTO - Tape and Reel
MCIMX515CJM6C 功能描述:處理器 - 專門應(yīng)用 iMX515 App Processor RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX515CJM6CR2 功能描述:處理器 - 專門應(yīng)用 i.MX51 32bit 800 MHz RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX515DJM8C 功能描述:處理器 - 專門應(yīng)用 iMX515 App Processor Extended Temp RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX515DJM8C 制造商:Freescale Semiconductor 功能描述:; LEADED PROCESS COMPATIBLE:YES; PEAK RE
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