參數(shù)資料
型號: MCZ33742EG
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類: CAN
英文描述: System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver
中文描述: 系統(tǒng)基礎(chǔ)芯片的增強型(SBC)的高速CAN收發(fā)器
文件頁數(shù): 18/65頁
文件大小: 1158K
代理商: MCZ33742EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
33742
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WDOG, INT) (CONTINUED)
Normal Request Mode Timeout
Normal Request Mode
t
NRTOUT
308
350
392
ms
Watchdog Period Stop Mode
Period 1
Period 2
Period 3
Period 4
t
WD-STOP
6.82
31.5
70
245
9.75
45
100
350
12.7
58.5
130
455
ms
Watchdog Period Accuracy
Normal and Standby Modes
Stop Mode
t
ACC
-12
- 30
12
30
%
Cyclic Sense FWU Timing Sleep and Stop Modes
Timing 1
Timing 2
Timing 3
Timing 4
Timing 5
Timing 6
Timing 7
Timing 8
t
CSFWU
3.22
6.47
12.9
25.9
51.8
66.8
134
271
4.6
9.25
18.5
37
74
95.5
191
388
5.98
12
24
48.1
96.2
124
248
504
ms
Cyclic Sense ON Time
Sleep and Stop Modes.
t
ON
200
350
500
μ
s
Cyclic Sense FWU Timing Accuracy
Sleep and Stop Modes
t
ACC
- 30
30
%
Delay Between SPI Command and HS Turn ON
(32)
Normal or Standby Mode, V
SUP
> 9.0 V
t
S-HSON
22
μ
s
Delay Between SPI Command and HS Turn OFF
(32)
Normal or Standby Mode, V
SUP
> 9.0 V
t
S-HSOFF
22
μ
s
Delay Between SPI and V2 Turn ON
(32)
Standby Mode
t
S-V2ON
9.0
22
μ
s
Delay Between SPI and V2 Turn OFF
(32)
Normal Mode
t
S-V2OFF
9.0
22
μ
s
Delay Between Normal Request and Normal Mode After Watchdog Trigger
Command
(32)
Normal Request Mode
t
S-NR2N
15
35
70
μ
s
Notes
32.
Delay starts at falling edge of clock cycle #8 of the SPI command and start of “Turn ON” or “Turn OFF” of HS or V2.
Table 6. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.75 V
V2
5.25 V, 5.5 V
V
SUP
18 V, and -40
°
C
T
A
125
°
C. Typical values
noted reflect the approximate parameter mean at T
A
= 25
°
C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
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