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參數(shù)資料
| 型號(hào)： | MCZ33742EG |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 元件分類： | CAN |
| 英文描述： | System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片的增強(qiáng)型（SBC）的高速CAN收發(fā)器 |
| 文件頁(yè)數(shù)： | 30/65頁(yè) |
| 文件大?。?/td> | 1158K |
| 代理商： | MCZ33742EG |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
30
33742
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
DEBUG MODE: HARDWARE AND SOFTWARE
DEBUG WITH THE 33742
When a SBC, and the MCU it serves, is used on the same
printed circuit board, both the MCU software and the 33742
operation must be debugged concurrently. The following
features permit system debugging by allowing the disabling
of the SBC internal software watchdog timer.
DEVICE POWER-UP, RESET PIN CONNECTED TO
VDD
The VDD voltage is available when the 33742 power-up
but the 33742 will not have received any SPI communication
to configure itself. Until set up by the system MCU, the 33742
will generate a reset every 350 ms until the part is configured.
To avoid continuous MCU hardware resets, the 33742’s RST
pin can be connected directly to VDD pin by a hardware
jumper.
DEBUG MODES WITH SOFTWARE WATCHDOG
DISABLED THOUGH SPI (NORMAL DEBUG,
STANDBY DEBUG, AND STOP DEBUG)
The software configurable watchdog can be disabled
through SPI. To set the watchdog disable while limiting the
risk of inadvertently disabling the watchdog timer during
normal 33742 operation, it is recommended that the disable
be done using the following sequence:
Step 1– Power down the SBC.
Step 2 – Power up the SBC. This sets the BATFAIL bit,
allowing the 33742 to enter Normal Request mode.
Step 3 – Write to the TIM1 sub register to allow the SBC to
enter Normal mode.
Step 4 – Write to the MCR register with data 0000. This
enables the debug mode. Complete SPI byte is
0001 0000.
Step 5 – Write to the MCR register normal debug. SPI byte
is 0001 x101.
Important
While in debug mode, the SBC can be used
without having to clear the watchdog on a regular basis to
facilitate software and hardware debug.
Step 6 – To leave the debug mode, write 0000 to the MCR
register.
At Step 2, the SBC is in Normal Request. Steps 3, 4, and 5
should be completed consecutively and within the 350 ms
time period of the Normal Request mode. If not, the 33742
will go into Reset mode and enter Normal Request again.
Figure 15
, page 30, illustrates debug mode selection.
Figure 15. Entering Debug Mode
When the SBC is operating in the debug mode and has
been set into Stop Debug or Sleep
mode, a wake-up causes
the 33742 to enter the Normal Request mode for 350 ms. To
avoid having the SBC generate an unwanted reset (enter
Reset mode), the next debug mode (Normal Debug or
Standby Debug) should be configured within the 350 ms time
window of the Normal Request mode.
To avoid entering debug mode after a power-up, first read
the BATFAIL bit (MCR read) and write 0000 into the MCR
register.
Figures 16 and 17, page
31
, show the detailed operation
of the SBC once the debug mode has been selected.
V
SUP
SPI
MCR (Step 4)
BATFAIL
VDD
Debug Mode
MCR (Step 5)
SPI: Read BATFAIL
MCR (Step 6)
33742 in Debug mode.
No Watchdog
33742 not in Debug mode.
Watchdog ON
TIM1(Step 3)
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| MCZ33742EGR2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SBC-E-HS-CAN RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| MCZ33742SEG | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SBC-E-HS-CAN RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| MCZ33742SEGR2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SBC-E-HS-CAN RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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| MCZ33780EG | 制造商:Freescale Semiconductor 功能描述:DUAL DBUS MASTER INTERFACE 16SOIC |
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