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參數(shù)資料
| 型號： | MCZ33742EG |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | CAN |
| 英文描述： | System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片的增強(qiáng)型（SBC）的高速CAN收發(fā)器 |
| 文件頁數(shù)： | 27/65頁 |
| 文件大?。?/td> | 1158K |
| 代理商： | MCZ33742EG |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
27
33742
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 11. Entering the Stop Mode
WATCHDOG SOFTWARE (RST AND WDOG)
(SELECTABLE WATCHDOG WINDOW OR
WATCHDOG TIME-OUT)
A watchdog is used in the SBC Normal and Standby
modes for monitoring the MCU operation. The watchdog
timer may be implemented as either a watchdog window or
watchdog time-out, selectable by SPI (TIM1 sub register, bit
WDW). Default operation is a watchdog window.
The watchdog period can be set from 10 ms to 350 ms
(TIM1 sub register, bits WDT0 and WDT1). When a watchdog
window is selected, the closed window is the first part of the
selected period, and the open window is the second part of
the period. (Refer to
Timing Register (TIM1 / 2)
beginning on
page
47
.)
The watchdog can only be cleared within the open window
time period. Any attempt to clear watchdog in the closed
window will generate a reset. The watchdog is cleared
addressing the TIM1 sub register using the SPI
RST PIN DESCRIPTION
A 33742 output is available to perform a reset of the MCU.
Reset can happen from:
VDD Falling Out of Range — f VDD falls below the reset
threshold (V
RSTTH
), the RST pin is pulled LOW until
VDD returns to the normal voltage.
Power-ON Reset — At 33742 power-on or wake-up from
Sleep mode, the RST pin is maintained LOW until VDD
is within its operation range.
Watchdog Time-out — If watchdog is not cleared, the
33742 will pull the RST pin LOW for the duration of the
reset time (t
RSTDUR
).
RST AND WDOG OPERATION
Table 8
describes watchdog and reset output modes of
operation. RST is activated in the event VDD fall or watchdog
is not triggered. WDOG output is active LOW as soon as RST
goes LOW and stays LOW as long as the watchdog is not
properly reset via SPI. The WDOG output pin is designed as
a push-pull structure that can drive off chip components
signaling, for instance, errant MCU operation.
Figure 12
illustrates the device behavior in the event the
TIM1 register in not properly accessed. In this case a
software reset occurs, and the WDOG pin is set LOW until
the TIM1 register is properly accessed.
SPI CS
SPI Stop/Sleep
Command
33742 in Normal
or Stand-by mode
33742 in Stop mode.
No I
DD
over I
DD-DGLT
33742 in Stop mode.
I
DD
over I
DD-DGLT
t
CS-STOP
tIDD-DGLT
Table 8. Watchdog and Reset Output Operation
Events
WDOG
Output
RST Output
Device Power-Up
LOW to HIGH
LOW to HIGH
VDD Normal, WDOG Properly Triggered
HIGH
HIGH
VDD < V
RSTTH
HIGH
LOW
WDOG Time-out Reached
LOW
(41)
LOW
Notes
41.
WDOG stays LOW until the TIM1 register
is properly addressed through SPI.
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| MCZ33742EGR2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SBC-E-HS-CAN RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| MCZ33742SEG | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SBC-E-HS-CAN RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| MCZ33742SEGR2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SBC-E-HS-CAN RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| MCZ33780EG | 功能描述:多路器開關(guān) IC DBUS MASTER RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開關(guān)數(shù)量:4 開啟電阻（最大值）:7 Ohms 開啟時間（最大值）: 關(guān)閉時間（最大值）: 傳播延遲時間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UQFN-16 |
| MCZ33780EG | 制造商:Freescale Semiconductor 功能描述:DUAL DBUS MASTER INTERFACE 16SOIC |
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