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參數(shù)資料
| 型號： | MCZ33742EG |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | CAN |
| 英文描述： | System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver |
| 中文描述： | 系統(tǒng)基礎(chǔ)芯片的增強型（SBC）的高速CAN收發(fā)器 |
| 文件頁數(shù)： | 42/65頁 |
| 文件大小： | 1158K |
| 代理商： | MCZ33742EG |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
42
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
SPI INTERFACE AND REGISTER DESCRIPTION
DATA FORMAT DESCRIPTION
Figure 27
illustrates an 8-bit byte corresponding to the
8 bits in a SPI register. The first three bits are used to identify
the internal SBC register address. Bit 4 is a read/write bit.
The last four bits are data sent from the MCU to the SBC or
read back from the 33742 to the MCU.
The state of the MISO has no significance during the write
operation. However, during a read operation the final four bits
of MISO have meaning; namely, they contain the content of
the accessed register.
Figure 27. Data Format Description.
REGISTER DESCRIPTIONS
The following tables in this section describe the SPI
register list and register bit meaning. Register reset values
are also described, along with the reset condition. A reset
condition is the condition causing the bit to be set at the reset
value.
Bit 7
Bit 5
Bit 3
Bit 4
Bit 2
Bit 6
Bit 1
Bit 0
A2
A0
D3
R/W
D2
A1
D1
D0
MISO
MOSI
Address
Data
Note
Read operation: R/W bit = logic [0]
Write operation: R/W = logic [1]
:
Table 13. Possible Reset Conditions
Condition
Name
Definition
33742 Reset
POR
Power-ON Reset
33742 Mode
Transition
NR2R
Normal Request to Reset Mode
NR2N
Normal Request to Normal Mode
NR2STB
Normal Request to Standby Mode
N2R
Normal to Reset Mode
STB2R
Standby to Reset Mode
STO2R
Stop to Reset Mode
STO2NR
Stop to Normal Request
33742 Mode
RESET
33742S in Reset Mode
Table 14. List of Registers
Register
Address
Formal Name
and Link
Comment and Use
Write
Read
MCR
$000
Mode Control Register (MCR)
on page 43
Selection for Normal, Standby, Sleep,
Stop, and Debug modes
BATFAIL, general failure, VDD pre-
warning, and Watchdog flag
RCR
$001
Reset Control Register (RCR)
on page 44
Configuration for reset voltage level, CAN Sleep and Stop modes
CAN
$010
CAN Register (CAN) on page
44
CAN slew rate, Sleep and Wake-Up
enable/disable modes, drive enable after
failure
CAN wake-up and CAN failure status bits
IOR
$011
Input Output Register (IOR)
on page 45
HS (high-side switch) control in Normal
and Standby mode
HS overtemperature bit, VSUP, and V2
LOW status
WUR
$100
on page 46
Control of wake-up input polarity
Wake-up input and real time Lx input
state
TIM
$101
Timing Register (TIM1 2) on
page 47
TIM1: Watchdog timing control, Watch-
dog Window (WDW) or Watchdog Tim-
eout (WTO) mode
TIM2: Cyclic Sense and Forced Wake-
Up timing selection
CANL and TXD failure reporting
LPC
$110
Low Power Control Register
(LPC) on page 49
Control HS periodic activation in Sleep
and Stop modes, Forced Wake-Up mode
activation, CAN-INT mode selection
CANH and RXD failure reporting
INTR
$111
Interrupt Register (INTR) on
page 51
Enable or Disable of Interrupts
Interrupt source
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