參數(shù)資料
型號: MCZ33742EG
廠商: 飛思卡爾半導體(中國)有限公司
元件分類: CAN
英文描述: System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver
中文描述: 系統(tǒng)基礎芯片的增強型(SBC)的高速CAN收發(fā)器
文件頁數(shù): 45/65頁
文件大?。?/td> 1158K
代理商: MCZ33742EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
45
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
HIGH-SPEED CAN TRANSCEIVER MODES
The MODE bit (D0) controls the state of the CAN interface, TXRX or Sleep mode (
Table 22
). SC0 bit (D1) defines the slew
rate when the CAN module is in TXRX, and it controls the wake-up option (wake-up enable or disable) when the CAN module is
in Sleep mode.
INPUT OUTPUT REGISTER (IOR)
Tables 24
through
26
contain the Input / Output Register information.
Table 25
provides information about information HS control
in Normal and Standby modes, while
Table 26
provides status bit information.
Table 22. CAN High-Speed Transceiver Modes
SC1
SC0
MODE
CAN Mode
(Pass 1.1)
0
0
0
CAN TXRX, Slew Rate 0
0
1
0
CAN TXRX, Slew Rate 1
1
0
0
CAN TXRX, Slew Rate 2
1
1
0
CAN TXRX, Slew Rate 3
x
1
1
CAN Sleep and CAN Wake-Up Disable
x
0
1
CAN Sleep and CAN Wake-Up Enable
x = Don’t care.
Table 23. CAN Register Status Bits
Name
Logic
Description
CANWU
0
No CAN wake-up occurred.
1
CAN wake-up occurred.
CAN-F
0
No CAN failure.
1
CAN failure
(55)
.
CAN-UF
0
Identified CAN failure
(55)
.
1
Non-identified CAN failure.
THERM-CUR
0
No overtemperature or overcurrent on CANH or CANL drivers.
1
Overtemperature or overcurrent on CANH or CANL drivers.
Notes
55.
Error bits are latched in the CAN register.
Table 24. Input / Output Register
IOR
R/W
D3
D2
D1
D0
$011b
W
HSON
R
V2LOW
HSOT
VSUPLOW
DEBUG
Reset Value
0
Reset Condition
(Write)
(56)
POR
Notes
56.
See
Table 13
, page
42
, for definitions of reset conditions.
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