參數資料
型號: MCZ33742EG
廠商: 飛思卡爾半導體(中國)有限公司
元件分類: CAN
英文描述: System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver
中文描述: 系統(tǒng)基礎芯片的增強型(SBC)的高速CAN收發(fā)器
文件頁數: 49/65頁
文件大?。?/td> 1158K
代理商: MCZ33742EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
49
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Figure 30. HS Operation When Cyclic Sense Is Selected
Table 34. TIM2 Control Bits
LOW POWER CONTROL REGISTER (LPC)
Tables 35
through
39
contain the Low Power Control Register information. The LPC register controls:
The state of HS in Stop and Sleep modes (HS permanently OFF or HS cyclic).
Enable or disable of the forced wake-up function (SBC automatic wake-up after time spent in Sleep or Stop modes; time is
defined by the TIM2 sub register).
Enable or disable the sense of the wake-up inputs (Lx) at the sampling point of the Cyclic Sense period (LX2HS bit). (Refer to
Reset Control Register (RCR) on page 44
for details of the LPC register setup required for proper cyclic sense or direct wake-
up operation.
The LPC register also reports the CANH and RXD diagnostic.
Cyclic Sense Timing, OFF Time
time
HS
Sample
10
μ
s
HS OFF
HS ON
Lx Sampling Point
Cyclic Sense Timing,
ON Time
CSP2
CSP1
CSP0
Cyclic Sense Timing (ms)
Parameter
0
0
0
4.6
Cyclic Sense/FWU Timing 1
0
0
1
9.25
Cyclic Sense/FWU Timing 2
0
1
0
18.5
Cyclic Sense/FWU Timing 3
0
1
1
37
Cyclic Sense/FWU Timing 4
1
0
0
74
Cyclic Sense/FWU Timing 5
1
0
1
95.5
Cyclic Sense/FWU Timing 6
1
1
0
191
Cyclic Sense/FWU Timing 7
1
1
1
388
Cyclic Sense/FWU Timing 8
Table 35. Low Power Control Register
LPC
R/W
D3
D2
D1
D0
$110b
W
LX2HS
FWU
CAN-INT
HSAUTO
R
CANH2VDD
CANH2BAT
CANH2GND
RXPR
Reset Value
0
0
0
0
Reset Condition
(Write)
(62)
POR, NR2R, N2R,
STB2R, STO2R
POR, NR2R, N2R,
STB2R, STO2R
POR, NR2R, N2R,
STB2R, STO2R
POR, NR2R, N2R,
STB2R, STO2R
Notes
62.
See
Table 13, page
42
, for definitions of reset conditions.
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