參數(shù)資料
型號(hào): MCZ33742EG
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類(lèi): CAN
英文描述: System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver
中文描述: 系統(tǒng)基礎(chǔ)芯片的增強(qiáng)型(SBC)的高速CAN收發(fā)器
文件頁(yè)數(shù): 43/65頁(yè)
文件大?。?/td> 1158K
代理商: MCZ33742EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
MODE CONTROL REGISTER (MCR)
Tables 15
through
17
describes the various Mode Control Registers.
Table 15. Mode Control Register
MCR
R/W
D3
D2
D1
D0
$000b
W
MCTR2
MCTR1
MCTR0
R
BATFAIL
(49)
VDDTEMP
GFAIL
WDRST
Reset Value
0
0
0
Reset Condition (Write)
(50)
POR, RESET
POR, RESET
POR, RESET
Notes
49.
50.
BATFAIL bit cannot be set by SPI. BATFAIL is set when VSUP falls below 3.0 V.
See
Table 13
page
42
, for definitions of reset conditions
Table 16. Mode Control Register Control Bits
MCTR
2
MCTR
1
MCTR
0
33742S Mode
Description
0
0
0
Enter/Exit Debug
Mode
To enter/exit Debug Mode, refer to detailed description in
Debug Mode: Hardware and
Software Debug with the 33742
, page
30
.
0
0
1
Normal
0
1
0
Standby
0
1
1
Stop, Watchdog OFF
(51)
0
1
1
Stop, Watchdog ON
(51)
1
0
0
Sleep
(52)
1
0
1
Normal
No Watchdog running. Debug Mode.
1
1
0
Standby
1
1
1
Stop
Notes
51.
52.
Watchdog ON or OFF depends on RCR bit D3.
Before entering Sleep mode, BATFAIL bit in MCR must be previously cleared (MCR read operation), and NOSTOP bit in RCR must be
previously set to logic [1].
Table 17. Mode Control Register Status Bits
Name
Logic
Description
BATFAIL
0
VSUP was not below V
BF
.
1
VSUP has been below V
BF
.
VDDTEMP
0
No overtemperature pre-warning.
1
Temperature pre-warning on VDD regulator (bit latched).
GFAIL
0
No failure.
1
CAN Failure or HS overtemperature or V2 low.
WDRST
0
No watchdog reset occurred.
1
Watchdog reset occurred.
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