參數(shù)資料
型號： MCZ33742EG
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類： CAN
英文描述： System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver
中文描述： 系統(tǒng)基礎(chǔ)芯片的增強型（SBC）的高速CAN收發(fā)器
文件頁數(shù)： 51/65頁
文件大?。?/td> 1158K
代理商： MCZ33742EG
Analog Integrated Circuit Device Data
Freescale Semiconductor
51
33742
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
INTERRUPT REGISTER (INTR)
Tables 40
through
42
contain the Interrupt Register information. The INTR register allows masking or enabling the interrupt
source. A read operation identifies the interrupt source.
Table 42
provides status bit information. The status bits of the INTR
register content are copies of the IOR, CAN, TIM, and LPC registers status content. To clear the Interrupt Register bits, the IOR,
CAN, TIM, and/or LPC registers must be cleared (read register) and the recovery condition must occur. Errors bits are latched
in the CAN register and the IOR register.
When the mask bit is set, the INT pin goes LOW if the appropriate condition occurs. Upon a wake-up condition from Stop mode
due to overcurrent detection (I
DDS-WU1
or I
DDS-WU2
), an INT pulse is generated; however, INTR register content remains at 0000
(not bit set into the INTR register).
Table 40. Interrupt Register
INTR
R/W
D3
D2
D1
D0
$111b
W
VSUPLOW
HSOT-V2LOW
V1TEMP
CANF
R
VSUPLOW
HSOT
V1TEMP
CANF
Reset Value
–
0
0
0
0
Reset Condition
(Write)
(65)
–
POR, RST
POR, RST
POR, RST
POR, RST
Notes
64.
If only HSOT V2LOW interrupt is selected (only bit D2 set in INTR register), reading INTR register bit D2 leads to two possibilities:
1. Bit D2 = 1: Interrupt source is HSOT.
2. Bit D2 = 0: Interrupt source is V2LOW.
HSOT and V2LOW bits status are available in the IOR register.
See Table 13, page
42
, for definitions of reset conditions.
65.
Table 41. Interrupt Register Control Bits
Name
Description
CANF
Mask bit for CAN failures.
VDDTEMP
Mask bit for VDD medium temperature
(pre-warning).
HSOT - V2LOW
Mask bit for HS overtemperature AND V
2LTH
< 4.0 V.
VSUPLOW
Mask bit for V
BF(EW)
< 5.8 V.
Table 42. Interrupt Register Status Bits
Name
Logic
Description
VSUPLOW
0
No V
BF(EW)
< 5.8 V.
1
V
BF(EW)
< 5.8 V.
HSOT
0
No HS overtemperature.
1
HS overtemperature.
VDDTEMP
0
No VDD medium temperature (pre-warning).
1
VDD medium temperature (pre-warning).
CANF
0
No CAN failure.
1
CAN failure.
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