參數(shù)資料
型號： MJ80C31U-36:D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER
文件頁數(shù)： 25/101頁
文件大小： 3398K
26
8168C-MCU Wireless-02/10
AT86RF212
The interrupt IRQ_4 has two meanings, depending on the current radio transceiver
state; refer to register 0x01 (TRX_STATUS). After P_ON, SLEEP, or RESET, the radio
transceiver issues an interrupt IRQ_4 (AWAKE_END) when it enters state TRX_OFF.
The second meaning is only valid for receive states. If the microcontroller initiates an
ED or CCA measurement, the completion of the measurement is indicated by interrupt
IRQ_4 (CCA_ED_DONE); refer to sections 6.5.4 and 6.6.4 for details.
After P_ON or RESET, all interrupts are disabled. During radio transceiver initialization,
it is recommended to enable IRQ_4 (AWAKE_END) to be notified once the TRX_OFF
state is entered. Note that AWAKE_END interrupt can usually not be seen when the
transceiver enters TRX_OFF state after RESET, because register 0x0E (IRQ_MASK) is
reset to mask all interrupts. In this case, state TRX_OFF is normally entered before the
microcontroller could modify the register.
The interrupt handling in Extended Operating Mode is described in section 5.2.5.
If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt
event can be read from IRQ_STATUS register, even if the interrupt itself is masked;
refer to Figure 4-18. However, in that case no timing information for this interrupt is
provided.
The IRQ pin polarity can be configured with register bit IRQ_POLARITY (register 0x04,
TRX_CTRL_1). The default behavior is active high, which means that pin IRQ = H
issues an interrupt request.
If the Frame Buffer Empty Indicator is enabled during Frame Buffer read access, the
IRQ pin has an alternative functionality; refer to section 9.6 for details.
A solution to monitor the IRQ_STATUS register (without clearing it) is described in
section 4.4.
4.7.2 Register Description
Register 0x0E (IRQ_MASK):
The IRQ_MASK register is used to enable or disable individual interrupts. An interrupt is
enabled if the corresponding bit is set to 1. All interrupts are disabled after power up
sequence (P_ON state) or reset (RESET state).
Table 4-16. Register 0x0E (IRQ_MASK)
Bit
7
6
5
4
Name
MASK_BAT_LOW
MASK_TRX_UR
MASK_AMI
MASK_
CCA_ED_DONE
Read/Write
R/W
Reset Value
0
Bit
3
2
1
0
Name
MASK_TRX_END
MASK_RX_START
MASK_
PLL_UNLOCK
MASK_PLL_LOCK
Read/Write
R/W
Reset Value
0
If an interrupt is enabled, it is recommended to read the interrupt status register 0x0F
(IRQ_STATUS) first to clear the history.
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