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參數(shù)資料
| 型號： | MJ80C31U-36:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER |
| 文件頁數(shù)： | 72/101頁 |
| 文件大?。?/td> | 3398K |
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95
8168C-MCU Wireless-02/10
AT86RF212
Scrambler
For data rates 1000 kbit/s and 400 kbit/s, additional chip scrambling is applied per
default in order to mitigate data dependent spectral properties. Scrambling can be
disabled if bit OQPSK_SCRAM_EN (register 0x0C, TRX_CTRL_2) is set to 0.
Energy Detection
The ED measurement time span is 8 symbol periods according to IEEE 802.15.4. For
frames operated at a higher data rate, the automated measurement duration (see
section 6.5.2) is reduced to 2 symbol periods taking reduced frame durations into
account. This means, the ED measurement time is 80 s for modes 200 kbit/s and 400
kbit/s, and 32 s for modes 500 kbit/s and 1000 kbit/s. For manually initiated ED
measurements in these modes, the measurement time is still 8 symbol periods.
Carrier Sense
For clear channel assessment, IEEE 802.15.4-2006 specifies several modes which may
either apply “energy above threshold” or “carrier sense” (CS) or a combination of both.
Since signals of the High Data Rate Modes are not compliant to IEEE 802.15.4-2006,
CS is not supported when the AT86RF212 is operating in these modes. However,
“energy above threshold” is supported.
Link Quality Indicator (LQI)
For the High Data Rate Modes, the link quality value does not contain useful
information and should be discarded.
7.1.5 Register Description
Register 0x0C (TRX_CTRL_2):
The TRX_CTRL_2 register controls the PHY mode settings. Note that during
configuration, the transceiver needs to be in state TRX_OFF.
Table 7-3. Register 0x0C (TRX_CTRL_2)
Bit
7
6
5
4
Name
RX_SAFE_MODE
TRX_OFF_AVDD_EN
OQPSK_SCRAM_EN
OQPSK_SUB1_RC_EN
Read/Write
R/W
Reset Value
0
1
0
Bit
3
2
1
0
Name
BPSK_OQPSK
SUB_MODE
OQPSK_DATA_RATE
Read/Write
R/W
Reset Value
0
1
0
Bit 7 – RX_SAFE_MODE
Refer to section 9.7.2.
Bit 6 – TRX_OFF_AVDD_EN
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