參數(shù)資料
型號： MJ80C31U-36:D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER
文件頁數(shù)： 51/101頁
文件大?。?/td> 3398K
76
8168C-MCU Wireless-02/10
AT86RF212
Table 6-16. Register 0x28 (IEEE_ADDR_4)
Bit
7
6
5
4
3
2
1
0
Name
IEEE_ADDR_4[7:0]
Read/Write
R/W
Reset Value
0
Register 0x29 (IEEE_ADDR_5):
This register contains bits [47:40] of the 64-bit IEEE extended address for Frame Filter
address recognition.
Table 6-17. Register 0x29 (IEEE_ADDR_5)
Bit
7
6
5
4
3
2
1
0
Name
IEEE_ADDR_5[7:0]
Read/Write
R/W
Reset Value
0
Register 0x2A (IEEE_ADDR_6):
This register contains bits [55:48] of the 64-bit IEEE extended address for Frame Filter
address recognition.
Table 6-18. Register 0x2A (IEEE_ADDR_6)
Bit
7
6
5
4
3
2
1
0
Name
IEEE_ADDR_6[7:0]
Read/Write
R/W
Reset Value
0
Register 0x2B (IEEE_ADDR_7):
This register contains bits [63:56] of the 64-bit IEEE extended address for Frame Filter
address recognition.
Table 6-19. Register 0x2B (IEEE_ADDR_7)
Bit
7
6
5
4
3
2
1
0
Name
IEEE_ADDR_7[7:0]
Read/Write
R/W
Reset Value
0
Register 0x2E (CSMA_SEED_1):
The CSMA_SEED_1 register is a control register for RX_AACK and contains a part of
the CSMA seed for the CSMA-CA algorithm, as well as control bits for the Frame Filter
and RX_AACK transaction.
Table 6-20. Register 0x2E (CSMA_SEED_1)
Bit
7
6
5
4
Name
AACK_FVN_MODE
AACK_SET_PD
AACK_DIS_ACK
Read/Write
R/W
Reset Value
0
1
0
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