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參數(shù)資料
| 型號： | MJ80C31U-36:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER |
| 文件頁數(shù)： | 71/101頁 |
| 文件大?。?/td> | 3398K |
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Figure 7-2. High Date Rate Frame Structure
Due to the overhead caused by the PPDU header and the FCS, the effective data rate
is less than the selected data rate, depending on the length of the PSDU. A graphical
representation of the effective data rate is shown in Figure 7-3.
Figure 7-3. Effective Data Rate of the O-QPSK Modes
0
20
40
60
80
100
120
0
100
200
300
400
500
600
700
800
900
B
[
k
b
it
/s
]
PSDU length in octets
Netto bit rate B
1000 kbit/s
500 kbit/s
250 kbit/s
400 kbit/s
200 kbit/s
100 kbit/s
Consequently, high data rate transmission is useful for large PSDU lengths due to the
higher effective data rate, or in order to reduce the power consumption of the system.
7.1.4.3 High Date Rate Mode Options
Reduced Acknowledgment Time
If register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1) is set, the
acknowledgment time is reduced to the duration of 2 symbol periods for 200 and 400
kbit/s, and to 3 symbol periods for 500 and 1000 kbit/s, refer to Table 5-24. Otherwise, it
defaults to 12 symbol periods according to IEEE 802.15.4.
Receiver Sensitivity Control
The different data rates between PPDU header (SHR and PHR) and PHY payload
(PSDU) cause a different sensitivity between header and payload. This can be adjusted
by defining sensitivity threshold levels of the receiver. With a sensitivity threshold level
set, the AT86RF212 does not synchronize to frames with an RSSI level below that
threshold. Refer to section 7.2.3 for a configuration of the sensitivity threshold with
register 0x15 (RX_SYN).
AT86RF212
8168C-MCU Wireless-02/10
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