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參數(shù)資料
| 型號： | MJ80C31U-36:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER |
| 文件頁數(shù)： | 7/101頁 |
| 文件大?。?/td> | 3398K |
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5.1.4.1 Power-on Procedure
The power-on procedure to P_ON state is shown in Figure 5-3.
Figure 5-3. Power-on Procedure to P_ON State
When the external supply voltage (VDD) is supplied to the AT86RF212, the radio
transceiver enables the crystal oscillator (XOSC) and the internal 1.8 V voltage
regulator for the digital domain (DVREG). After tTR1, the master clock signal is available
at pin 17 (CLKM) at a default rate of 1 MHz. If CLKM is available, the SPI has already
been enabled and can be used to control the transceiver. As long as no state change
towards state TRX_OFF is performed, the radio transceiver remains in P_ON state.
5.1.4.2 Wake-up Procedure
The wake-up procedure from SLEEP state is shown in Figure 5-4.
Figure 5-4. Wake-up Procedure from SLEEP State
The radio transceiver’s SLEEP state is left by releasing pin SLP_TR to logic low. This
restarts the XOSC and DVREG. After tTR2, the radio transceiver enters TRX_OFF state.
The internal clock signal is available and provided to pin 17 (CLKM) if enabled.
This procedure is similar to power-on, however, the radio transceiver automatically
ends in TRX_OFF state. During this, the filter-tuning network (FTN) calibration is
performed. Entering TRX_OFF state is signaled by IRQ_4 (AWAKE_END) if this
interrupt was enabled by the appropriate mask register bit.
5.1.4.3 State Change from TRX_OFF to PLL_ON / RX_ON
The transition from TRX_OFF to PLL_ON or RX_ON state and further to RX_ON or
PLL_ON is shown in Figure 5-5.
AT86RF212
8168C-MCU Wireless-02/10
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