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參數(shù)資料
| 型號(hào)： | MJ80C31U-36:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER |
| 文件頁(yè)數(shù)： | 32/101頁(yè) |
| 文件大小： | 3398K |
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59
8168C-MCU Wireless-02/10
AT86RF212
The TRX_END interrupt is always generated after completing a TX_ARET transaction.
After that, the return code can be read from subfield TRAC_STATUS (register 0x02,
TRX_STATE).
Several interrupts are automatically suppressed by the radio transceiver during
TX_ARET transaction. In contrast to section 6.6, the CCA algorithm (part of CSMA-CA)
does not generate interrupt IRQ_4 (CCA_ED_DONE). Furthermore, the interrupts
RX_START and AMI are not generated during the TX_ARET acknowledgment receive
process.
5.2.6 Register Description
Register Summary
The following registers control the Extended Operating Mode.
Table 5-16. Extended Operating Mode Register Summary
Reg.-Addr.
Register Name
Description
0x01
TRX_STATUS
Radio transceiver status, CCA result
0x02
TRX_STATE
Radio transceiver state control, TX_ARET status
0x04
TRX_CTRL_1
TX_AUTO_CRC_ON
0x08
PHY_CC_CCA
CCA mode control, see section 6.6.6
0x09
CCA_THRES
CCA ED threshold settings, see section 6.6.6
0x17
XAH_CTRL_1
RX_AACK control
0x20
…
0x2B
Frame Filter configuration
-
Short address, PAN ID, and IEEE address
-
See section 6.2.3
0x2C
XAH_CTRL_0
TX_ARET control, retries value control
0x2D
CSMA_SEED_0
CSMA-CA seed value
0x2E
CSMA_SEED_1
CSMA-CA seed value, RX_AACK control
0x2F
CSMA_BE
CSMA-CA backoff exponent control
Register 0x01 (TRX_STATUS):
The read-only register TRX_STATUS provides the current state of the radio transceiver.
A state change is initiated by writing a state transition command to register bits
TRX_CMD (register 0x02, TRX_STATE).
Table 5-17. Register 0x01 (TRX_STATUS)
Bit
7
6
5
4
Name
CCA_DONE
CCA_STATUS
Reserved
TRX_STATUS[4]
Read/Write
R
Reset Value
0
Bit
3
2
1
0
Name
TRX_STATUS[3]
TRX_STATUS[2]
TRX_STATUS[1]
TRX_STATUS[0]
Read/Write
R
Reset Value
0
Bit 7:6 – CCA_DONE, CCA_STATUS
Refer to section 6.6.6; not updated in Extended Operating Mode.
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