參數(shù)資料
型號(hào)： MJ80C31U-36:D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER
文件頁(yè)數(shù)： 89/101頁(yè)
文件大?。?/td> 3398K
111
8168C-MCU Wireless-02/10
AT86RF212
7.4.3 Interrupt Handling
Access conflicts may occur when reading and writing data simultaneously at the
independent ports of the Frame Buffer, TX/RX BBP and SPI. These ports have their
own address counter that points to the Frame Buffer’s current address.
Access violations may cause data corruption and are indicated by IRQ_6 (TRX_UR)
interrupt when using the Frame Buffer access mode. Note that access violations are not
indicated when using the SRAM access mode.
While receiving a frame, first the data need to be stored in the Frame Buffer before
reading it. This can be ensured by accessing the Frame Buffer at least 8 symbols
(BPSK) or 2 symbols (O-QPSK) after interrupt IRQ_2 (RX_START). When reading the
frame data continuously, the SPI data rate shall be lower than the current TRX bit rate
to ensure no underrun interrupt occurs. To avoid access conflicts and to simplify the
Frame Buffer read access, Frame Buffer Empty indication may be used; for details,
refer to section 9.6.
When writing data to the Frame Buffer during frame transmission, the SPI data rate
shall be higher than the PHY data rate avoiding underrun. The first byte of the PSDU
data must be available in the Frame Buffer before SFD transmission is complete, which
takes 41 symbol periods for BPSK (1 symbol PA ramp up + 40 symbols SHR) and 11
symbol periods for O-QPSK (1 symbol PA ramp up + 10 symbols SHR) from the rising
edge of SLP_TR pin (see Figure 5-2).
Notes
Interrupt IRQ_6 (TRX_UR) is valid 2 octets after IRQ_2 (RX_START).
If a Frame Buffer read access is not finished until a new frame is received, a
TRX_UR interrupt occurs. Nevertheless, the old frame data can be read if the SPI
data rate is higher than the effective PHY data rate. A minimum SPI clock rate of
1 MHz is recommended in this case. Finally, the microcontroller should check the
integrity of the transferred frame data by calculating the FCS.
7.5 Voltage Regulators (AVREG, DVREG)
The main features of the Voltage Regulator blocks are:
Bandgap stabilized 1.8 V supply for analog and digital domain
Low dropout (LDO) voltage regulator
Configurable for usage of an external voltage regulator
7.5.1 Overview
The internal voltage regulators supply a stabilized voltage to the AT86RF212. The
AVREG provides the regulated 1.8 V supply voltage for the analog domain and the
DVREG supplies the 1.8 V supply voltage for the digital domain.
A simplified schematic of the internal analog voltage regulator is shown in Figure 7-12.
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