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參數(shù)資料
| 型號(hào)： | MJ80C31U-36:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER |
| 文件頁(yè)數(shù)： | 31/101頁(yè) |
| 文件大?。?/td> | 3398K |
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58
After that, the AT86RF212 switches to receive mode and expects an acknowledgement
response, which is indicated by register subfield TRAC_STATUS (register 0x02,
TRX_STATE) set to SUCCESS_WAIT_FOR_ACK. After a period of aTurnaroundTime
+ aUnitBackoff, the transmission of the ACK frame must have started. During the entire
transaction, including frame transmit, wait for ACK, and ACK receive, the radio
transceiver status register TRX_STATUS (register 0x01, TRX_STATUS) signals
BUSY_TX_ARET.
A successful reception of the acknowledgment frame is indicated by interrupt IRQ_3
(TRX_END). The status register TRX_STATUS (register 0x01, TRX_STATUS) changes
back to TX_ARET_ON. At the same time, register TRAC_STATUS changes to
SUCCESS or to SUCCESS_DATA_PENDING if the “Frame Pending” subfield of the
acknowledgment frame was set to 1.
Figure 5-13. Exemplary Timing of a TX_ARET Transaction (without Pending Data Bit set in ACK Frame)
Frame
on
Ai
r
5.2.5 Interrupt Handling
The interrupt handling in the Extended Operating Mode is similar to the Basic Operating
Mode. Interrupts can be enabled by setting the appropriate bit in register 0x0E
(IRQ_MASK).
For RX_AACK and TX_ARET, the following interrupts inform about the status of a
frame reception and transmission:
IRQ_2 (RX_START)
IRQ_3 (TRX_END)
IRQ_5 (AMI)
For RX_AACK mode, it is recommended to enable only interrupt IRQ_3 (TRX_END).
This interrupt is issued only if the Frame Filter (see section 6.2) reports a matching
address and the FCS is valid (see section 6.3). The usage of other interrupts is
optional.
On reception of a frame, the RX_START interrupt indicates the detection of a correct
synchronization header (SHR) and a non-zero PHY header (PHR). This interrupt is
issued after the PHR. AMI indicates address match, refer to filter rules in section 6.2.
AT86RF212
8168C-MCU Wireless-02/10
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