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參數(shù)資料
| 型號： | MK68901 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Multifunction Peripheral(多功能外圍電路) |
| 中文描述： | 多功能外圍（多功能外圍電路） |
| 文件頁數(shù)： | 10/33頁 |
| 文件大?。?/td> | 313K |
| 代理商： | MK68901 |
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In the delay mode, the prescaler is always active.
A count pulse will be applied to the main timer unit
each time the prescribed number of timer clock cy-
cles haselapsed. Thus, if theprescaler is program-
med to divide by ten, a count pulse will be applied
to the main counter every ten cycles of the timer
clock.
Each timeacount pulseisapplied tothe maincoun-
ter, it willdecrement its contents. The main counter
is initially loaded by writingto theTimer Data Regis-
ter. Each count pulse will cause the current count to
decrement. When thetimerhas decremented down
to ”01” , the next count pulse will not cause it to de-
crement to ”00”. Instead, the next count pulse will
cause the timer to be reloaded from the Timer Data
Register.Additionally, a ”Timeout”pulse willbepro-
duced. This Time Out pulse is coupled to the timer
interrupt channel, and, ifthat channel isenabled, an
interrupt willbe produced. TheTime Outpulse is al-
so coupled to the timeroutput pin and will cause the
pin to change states. The output will remain in this
newstateuntilthenextTimeOutpulse occurs.Thus
the output will complete one full cycle for each two
Time Out pulses.
If, for example, the prescaler were programmed to
divideby ten,and the TimerDataRegister wereloa-
ded with 100 (decimal), themain counter would de-
crement once for everytencyclesofthetimerclock.
ATimeOutpulsewilloccur(henceaninterrupt ifthat
channel is enabled) every 1000 cycles of the timer
clock, and the timer outputwill complete one fullcy-
cleevery 2000 cycles of thetimer clock.
The main counter is an 8-bit binary down counter. It
maybe readat any time by reading theTimer Data
Register. The information read is the information
last clockedintothetimer read registerwhenthe DS
pinhad lastgone high prior tothecurrent readcycle.
When written,data isloaded intotheTimerDataRe-
gister, and the main counter, ifthe timer is stopped.
If the Timer Data Register is written while the timer
is running, the newword is notloaded into the timer
until it counts through H”01”. However, if the timer
iswritten while itis counting through H”01”, an inde-
terminatevalue willbe writteninto thetimer constant
register. This may becircumvented byensuring that
the data register is not written when the count is
H”01”.
If the main counter is loaded with ”01”, a Time Out
Pulse will occur every time the prescaler presents
a count pulse to the main counter. If loaded with
”00”, a Time Out pulse will occur every 256 count
pulses.
Figure 12 :
Timer A and B Control Registers.
*
Unused bits : read as zeros.
V000359
MK68901
10/33
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