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參數(shù)資料
| 型號： | MK68901 |
| 廠商： | 意法半導體 |
| 英文描述： | Multifunction Peripheral(多功能外圍電路) |
| 中文描述： | 多功能外圍（多功能外圍電路） |
| 文件頁數(shù)： | 19/33頁 |
| 文件大?。?/td> | 313K |
| 代理商： | MK68901 |
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Unused bits in the sync character register are ze-
roed out ; therefore, word length should be set up
prior to writing the sync word in some cases. Sync
word length is the word length plus one when parity
is enabled. The user has to determine the parity of
the syncwordwhenthe wordlengthisnot 8bits.The
MK68901 MFP does notadd a parity bit to the sync
word if the word length is less than 8 bits. The extra
bit in the sync word is transmitted as the parity bit.
With a word length of eight, and parity selected, the
parity bitfor thesync wordiscomputed an added on
by theMK68901 MFP.
RR RECEIVER READY
RR is asserted when the Buffer Full bit is set in the
RSR unless a parity error or frame error is detected
by thereceiver.
TR TRANSMITTER READY
TR isasserted when the Buffer Emptybit isset in the
TSR unless a break is currently being transmitted.
REGISTER ACCESSES
All register accesses are dependent on CLK as
shownin thetimingdiagrams. To read a register, CS
andDSmustbeasserted,andR/Wmustbyhigh.The
internal read control signal is essentially the combi-
nation of CS, DS, and RD/WR. Thus, theread ope-
ration will begin when CS and DS go activeand will
endwheneitherCSorDSgoesinactive.Theaddress
busmust be stable priorto the start of the operation
andmustremain stableuntil theend oftheoperation.
Unlessa read operation orinterrupt acknowledge cy-
cleis in progress the data bus(D
0
-D
7
) will remain in
the tri-state condition.
To write aregister, CSand DSmust beassertedand
R/W must be low. The address mustbe stable prior
to the start of the operation and must remain stable
untilthe end of theoperation. Afterthe MK68901 as-
sertsDTACK,theCPUnegates DS,.Atthistime,the
MFPlatchesthedata bus and writesthecontents in-
to the appropriate register. Also when DS is nega-
ted, the MFP rescinds DTACK.
For an interrupt acknowledge, the operation starts
when IACK goes low, and ends when IACK goes
high. The data busis tri-stated when either IACK or
DS goes high.
When CS or IACK are asserted the MFP starts an
internal cycle. DS is needed to enable the address
and data buffers. It is recommended taht CS and
IACK be gated by DS so that DS is always present
whenever an MFP bus cycle starts.
MK68901
19/33
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| MK6-8-K | 制造商:MEDER Electronic 功能描述: |
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