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參數(shù)資料
| 型號： | MK68901 |
| 廠商： | 意法半導體 |
| 英文描述： | Multifunction Peripheral(多功能外圍電路) |
| 中文描述： | 多功能外圍（多功能外圍電路） |
| 文件頁數(shù)： | 14/33頁 |
| 文件大?。?/td> | 313K |
| 代理商： | MK68901 |
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÷
16/
÷
1 : Whenthisbit iszero, data willbe clocked
into and out of the receiver and transmit-
ter at the frequency of their respective
clocks.Whenthisbitis loaded with aone,
datawillbe clockedinto andoutofthere-
ceiver and transmitter at one sixteenth
the frequency of their respective clocks.
Additionally, when placed inthedivide by
sixteenmode, thereceiverdatatransition
resynchronization logic will be enabled.
WL0-WL1 :Word Length Control. These two bitsset
thelength of the data word (exclusive of
start bits, stop bits, and parity bits as fol-
lows:
ST0-ST1 :Start/stop bit control (format control).
These two bits set theformat as follows
:
PARITY : Parity Enabled. When set (”1”), parity will
be checked by thereceiver, parity will be
calculated, anda parity bitwillbe inserted
bythe transmitter. When cleared (”0”) no
paritycheckwillbemade andnoparitybit
will be inserted for transmission.
Forawordlength of8theMFPcalculates
the parity and appends it when transmit-
ting a sync character. For shorter
lengths, the parity must be stored in the
Sync Character Register (SCR) along
with the sync character.
Even-Odd. When set (”1”), even parity
will be used if parity is enabled. When
cleared(”0”), odd paritywill beusedifpa-
rity is enabled.
Note that the synchronous or asynchronous format
maybeselectedindependently ofa
÷
1or
÷
16clock.
Thus it is possible to clockdata synchronously into
the device but still use start and stop bits. In this
mode, all normal asynchronous format features still
apply. Data will be shifted in after a start bit is en-
countered, and a stop bit will be checked to deter-
mine proper framing. If a transmit underrun condi-
tion occurs, the output will be placed in a marking
state, etc. It is conversely possible to clock data in
asynchronously using a synchronous format. There
isdata transitiondetection logicbuiltintothereceive
clock circuitry which will re-synchronize the internal
shift clock on each data transition so that, with suf-
ficientyfrequent data transitions,startbitsarenotre-
quired. In thismode, allother commonsynchronous
features function normally. Thisre-synchronization
logic is only active in
÷
16 clock mode.
E/O :
RECEIVER
The receiver section of the USART is configured by
theUCR as previously described. The status of the
receiver can be determined by reading and writing
to the Receiver Status Register (RSR). The RSR is
configured as follows :
Figure 17 :
USART Control Register (UCR).
WL1 WL0
0
0
1
1
Word Length
8 Bits
7 Bits
6 Bits
5 Bits
0
1
0
1
ST1
0
0
1
1
ST0
0
0
1
StartBits
0
1
1
1
StopBits
0
1
1
1
/
2
2
Format
SYNC
ASYNC
ASYNC
ASYNC
V000363
MK68901
14/33
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