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參數(shù)資料
| 型號(hào)： | MK68901 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Multifunction Peripheral(多功能外圍電路) |
| 中文描述： | 多功能外圍（多功能外圍電路） |
| 文件頁(yè)數(shù)： | 22/33頁(yè) |
| 文件大?。?/td> | 313K |
| 代理商： | MK68901 |
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AC ELECTRICAL CHARACTERISTICS
(continued)
(V
CC
= 5.0Vdc
±
5%, GND = 0Vdc, T
A
= 0
°
Cto 70
°
C)
Value
MK68901-4
Min.
110
250
2
MK68901-5
Min.
90
200
1.8
Number
Characteristic
Max.
Max.
Unit
Fig.
Note
33
34
35
36
Timer Clock High Time
Timer Clock Cycle Time
RESET Low Time
Delay to Falling INTR from External Interrupt
Active Transition
Transmitter Internal Interrupt Delay from Falling
Edge of TC
Receiver Buffer Full Interrupt Transition Delay
from Rising Edge of RC
Receiver Error Interrupt Transition Delay from
Falling Edge of RC
Serial in Set Up Time to Rising Edge of RC
(divide by one only)
Data Hold Time from Rising Edge of RC
(divide by one only)
Serial Output Data Valid from Falling Edge of TC
(
÷
1)
Transmitter Clock Low Time
Transmitter Clock High Time
Transmitter Clock Cycle Time
Receiver Clock Low Time
Receiver Clock High Time
Receiver Clock Cycle Time
CS, IACK, DS Width Low
Serial Output Data Valid from Falling Edge of TC
(
÷
16)
ns
ns
μ
s
29
29
30
1000
1000
380
380
ns
25
37
550
550
ns
28
38
800
800
ns
27
39
800
800
ns
27
40
80
70
ns
27
41
350
325
ns
27
42
440
420
ns
28
43
44
45
46
47
48
49
50
500
500
1.05
500
500
1.05
450
450
0.95
450
450
0.95
ns
ns
μ
s
ns
ns
μ
s
28
28
28
27
27
27
29
∞
∞
∞
80
∞
80
T
CLK
2
490
370
ns
28
Notes :
1. IEO only goes low if no acknowedgeable interrupt is
pending. If IEO goeslow,DTACK and the data bus re-
maintri-stated.
2. T
CLK
refers to the clock applied to the MFP CLK input
pin. t
CLK
refers to the timer clock signal, regardless of
whetherthatsignal comesfromtheXTAL1/XTAL2crys-
talclock inputsor theTAI or TBI timerinputs.
3. Ifthesetup timeis not met, CSorIACK willnotbereco-
gnized until thenext fallingCLK.
4. If thissetup timeis met (for consecutive cycles), the mi-
nimumhold-off time of oneclock cyclewillbe obtained.
If notmet,the hold-off willbe two clock cycles.
5. CS islatchedinternally, therefore if spec’s 1 and 24 are
metthen CS may bereasserted beforetherisingclock
andstill terminatethe currentbuscycle.Thenewbuscy-
cle willbedelayed by theMK68901 until all appropriate
internal operations havecompleted.
6. Although CS and DTACK are synchronized with the
clock, thedataoutduring aread cycle is asynchronous
to theclock, relying only on CS fortiming.
7. Spec. 30applies to timeroutputs TAO and TBOonly.
MK68901
22/33
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