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參數(shù)資料
| 型號： | MK68901 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Multifunction Peripheral(多功能外圍電路) |
| 中文描述： | 多功能外圍（多功能外圍電路） |
| 文件頁數(shù)： | 16/33頁 |
| 文件大?。?/td> | 313K |
| 代理商： | MK68901 |
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Therearetwointerruptchannels associatedwiththe
receiver. Onechannel is used for the normal Buffer
Full condition, while the other channel is used whe-
never an error condition occurs. Only one interrupt
is generated per word received, but dedicating two
channelsallows separatevectors : one for the nor-
mal condition, and one for an error condition. If the
error channel is disabled, an interrupt will be gen-e-
rated via the Butter Full Channel, whether the word
received is normal or in error. Those conditions
which produce an interrupt via the error channel
are : Overrun, Parity Error, Frame Error, Sync
Found, and Break. If a received word has an error
associated with it, and the error interrupt channel is
enabled,an interrupt will occur ontheerror channel
only.
Each timea word istransferred into thereceive buf-
fer, a corresponding set of flags is latched into the
RSR. No flags(except CIP) are allowed to change
until the data word has been read from the receive
buffer.Reading the receive buffer allowsa newdata
word to be transferred to the receive buffer when it
is received. Thus one shouldfirstreadtheRSRthen
read the receive buffer (UDR) to ensure that the
flagsjustread matchthe datawordjust read. Ifdone
in the reverse order, it is possible that subsequent
to reading thedata wordfrom thereceivebuffer, but
prior to reading the RSR, a new word may be recei-
ved and transferred to the receive buffer and, with
it, its associated flags latched into the RSR. Thus,
when theRSRis read, thoseflags may actuallycor-
respond to a different data word. It is good practice,
also to read the RSR prior to a data read as, when
an overrunerror occurs, thereceiverwill not assem-
ble new characters until the RSRhas been read.
As previously stated, when overrun occurs, the OE
flag will not be set and the associated interrupt will
not be generated until the receive buffer has been
read. If a break occurs, and the receive buffer has
not yetbeen read, only the Bflag will be set (OEwill
not be set). Again, this flag will not be set until the
last valid word has been read fromthe receive buf-
fer. If the break condition ends and another whole
data word is received before the receive buffer is
read, both the B and OE flags will be set once the
receive buffer is read.
If a break occurs while the OEflag is set, the Bflag
willalso be set.
A break generates an interrupt when the condition
occurs and again when the condition ends. If the
break condition ends before it is acknowledged by
reading the RSR, the receiver error interrupt indica-
tingend of break willbe generated once the RSR is
read.
Anytime the asynchronous format is selected, start
bit detection is enabled. New data is notshifted into
theshift register until a zero bit is detected. If a
÷
16
clock is selected, along with the asynchronous for-
mat, false start bit detection is also enabled. Any
transition has tobestablefor 3positive going edges
ofthereceive clocktobecalleda validtransition.For
a start bit to be good, a valid 0-1 transition must not
occur for 8 positive clock transitions after the initial
valid 1-0 transition.
Aftera good start bit has been detected, valid tran-
sitions in the data are checked for continously.
When a valid transition is detected, the counter is
forcedtostatezero,andnomoretransitionchecking
isstarted untilstatefour.At stateeight, the”previous
state” of the transition checking logic is clocked into
thereceiver.
As a result of this resynchronization logic, it is pos-
sible to run with asynchronous clocks without start
and stop bits if there are sufficient valid transitions
in the data stream. This logic also makes the unit
more tolerant of clock skew for normal asynchro-
nouscommunications than adevice which employs
only start bit synchronization.
Figure 19 :
Transmitter Status Register (TSR).
V000365
MK68901
16/33
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