![](http://datasheet.mmic.net.cn/330000/MK68901_datasheet_16440041/MK68901_18.png)
Figure 20 :
SYNC Character Register.
Enable (XE) is set will alter the output
stateuntilENDisfalse.These bitsshould
be set prior to enabling the transmitter.
The state of these bits determine the
state of thefirst transmitted character af-
ter the transmitter is enabled. If the high
impedance mode was selected prior to
thetransmitter being enabled, thefirstbit
transmitted is indeterminate.
Transmitter Enable. This control bit is u-
sed to enable or disable the transmitter.
When set, the transmitter is enabled.
Whencleared, the transmitter will be di-
sabled. If disabled, any word currently in
the output register will continue to be
transmitted when XE is cleared, the
transmitter will turn off at the end of the
break character boundary, and noend of
break stopbit istransmitted. Thetransmit
clock must be running before the trans-
mitter is enabledA ”one”bit always pre-
cedes the firstwordout of thetransmitter
after the transmitter is enabled. There is
a delay between the time the transmitter
enable bitiswritten anwhenthetransmit-
ter reset goes low ; therefore, the H & L
bits should be written with the desired
state prior to enabling the transmitter.
Likethe receiver section, there are two separate in-
terrupt channels associated with the transmitter.
The buffer Empty condition causes an interrupt via
one channel, while the Underrun and END condi-
tionswill cause aninterrupt viathe second channel.
Whenunderrun occurs in the synchronous format,
the character in the SCR will be transmitted until a
new words is loaded into the transmit buffer. In the
asynchronous format, a ”Mark” will be continuously
transmitted when underrun occurs.
The transmit buffer can be loaded prior to enabling
the transmitter. When the transmitter is disabled,
anycharacter currently in theprocess ofbeingtrans-
mitted will continue to conclusion, but anycharacter
inthe transmit buffer will not be transmitted and will
remain in the buffer. Thus no buffer empty interrupt
willoccurnorwilltheBEflag beste.Ifthe bufferwere
already empty, the BEflag would be set and would
remain set. Whenthe transmitter isdisabled with a
character intheoutputregister butwith nocharacter
XE :
in the transmit buffer, an Underrun Error will not oc-
curwhen the character inprogress concludes.
Often it is necessary to send a break for some par-
ticular period. To aid in timing a break transmission,
a transmission, a transmit error interrupt will be ge-
nerated at every normal character boundary time
during a breaktransmission. The status register in-
formation is unaffected by this error condition inter-
rupt. Itshouldbenotedthatanunderrun error,ifpre-
sent, must be cleared from the TSR, and the inter-
rupt pending register must be cleared of pending
transmitter errors at the beginning of the break
transmission ornointerrupts willbegenerated atthe
character boundary time.
Itthesynchronous formatisselected, thesyncchar-
acter should be loaded intotheSync Character Re-
gister (SCR) as shouwn in figure 20. This character
is compared to the received serial data during a
Search, and will be continuously transmitted during
an underrun condition.
Allflags in theRSR orTSR will continue to function
as described whether their associated interrupt
channel is disabled or enabled. All interrupt chan-
nels areedge triggered and, in many cases,itis the
actualoutput ofa flagbit or flag bitswhichiscoupled
to the interrupt channel. thus, if a normal interrupt
producing condition occurswhile theinterrupt chan-
nelisdisabled, nointerrupt wouldbeproduced even
if the channel was subsequently enabled, because
a transition did notoccur whiletheinterrupt channel
was enabled. that particular flag bit would have to
occur asecond timebeforeanother ”edge” waspro-
duced, causing aninterrupt to be generated.
Error conditions in the USART are determined by
monitoring the Receive Status Register and the
Transmitter Status Register. These error conditions
are only valid for each word boundary and are not
latched. Whenexecuting block tranfers or data, it is
necessary to save any errors so that they can be
checked at the end of a block. In order to saveerror
conditions during data transfer, the MK68901 MFP
interrupt controller maybeusedbyenablingerror in-
terrupt for the desired channel (Receive error or
Transmit error) and by masking these bitsoff.Once
thetranfer iscomplete, theInterrupt Pending Regis-
ter can be polled, to determine the precence of a
pending errorinterrupt, and therefore an error.
V000366
MK68901
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