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參數(shù)資料
| 型號(hào)： | MK68901 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Multifunction Peripheral(多功能外圍電路) |
| 中文描述： | 多功能外圍（多功能外圍電路） |
| 文件頁(yè)數(shù)： | 17/33頁(yè) |
| 文件大?。?/td> | 313K |
| 代理商： | MK68901 |
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TRANSMITTER
The transmitter section of the USARTis configured
as to format, word length, etc. by the UCR, as pre-
viouslydescribed. The status of the transmitter can
be determined by reading orwriting the Transmitter
StatusRegister (TSR).TheTRSisconfigured asfol-
lows :
BE :
Buffer Empty. This status bit is set when
theword inthetransmit buffer is transfer-
red to the output shift register and thus
thetransmit buffer may be reloaded with
the next data word. The flag is cleared
when thetransmitbufferis reloaded. The
transmit buffer is loaded bywriting to the
UDR.
UE :
This bit is set when the last word has
been shifted out of the transmit shift re-
gister before a new word has been loa-
ded into the transmit buffer. It is not ne-
cessarytoclearthisbitbeforeloading the
UDR.
Thisbit maybe cleared by eitherreading
the TSR or by disabling the transmitter.
After the setting of the UE bit, one full
transmitter clock cycleis required before
this bit can be cleared by a read. The ti-
ming insome systemsmay allow a read
of the TSRbefore therequired clock cy-
cle has been completed. This would re-
sult in the UE bit not being cleared until
thefollowing read. Toavoidthis problem,
a dummyread oftheTSR shouldbe per-
formed at the end of he UE service rou-
tine.
Only one underrun error may be genera-
tedbetween loadsofthe UDRregardless
of the number of transmitter clock cycles
between UDR loads.
AT :
Thisbitcausesthereceivertobeenabled
at the end of the transmission of the last
word in the transmitter if the transmitter
has beendisabled.
END :
Endor Transmission. When thetransmit-
teristurned offwith acharacter stillinthe
output shift register, transmission will
continue until that character is shifted
out. Once it has cleared theoutput regis-
ter,theENDbit will be set.Ifnocharacter
is being transmitted when thetransmitter
is disabled,thetransmitter willstopat the
nextrisingedgeof theinternal shiftclock,
and END will immediately be set. The
END bit is cleared by re-enabling the
transmitter.
Break. This controlbit will cause a break
to betransmitted. Whena ”1”iswritten to
the Bbitof the TSR,a break willbe trans-
mitted upon completion of the character
(if any) currently being transmitted. A
breakwill continue to be transmitted until
the Bbit is cleared by writing a ”0” tothis
bit of theTSR. At that time,normal trans-
mission will resume. The B bit has no
function inthe synchronous format. Set-
ting the ”B”bitto a onekeepsthe”BE”bit
from being set to a one. So, if therewere
a word in the buffer at the start of break,
it would remain there until the end of
break, at which timeitwouldbe transmit-
ted (if the transmitter is still enabled). If
the buffer were not full at the start of
break, it could be written at anytime du-
ring thebreak. Ifthebuffer isemptyatthe
endofbreak, the underrun flagwillbeset
(unlessthe transmitter is disabled).
The BREAK bit cannot be set until the
transmitter has been enabled and the
transmitter has had sufficient time (one
clock cycle) to perform the internal reset
and initialization functions.
High and Low.These twocontrol bits are
used to configure the transmitter output,
when the transmitter is disabled, as fol-
lows :
H L Output State
0 0 Hi-Z
0 1 Low (”0”)
1 0 High
1 1 Loop-Connects transmitter output to
receiver input, and TC to Receiver Clock
(RC andSIare notused ;theyarebypas-
sed internally). In loop back mode, trans-
mitter output goes high when disabled.
B :
H,L :
Altering these two bits after Transmitter
MK68901
17/33
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