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參數(shù)資料
| 型號： | MK68901 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Multifunction Peripheral(多功能外圍電路) |
| 中文描述： | 多功能外圍（多功能外圍電路） |
| 文件頁數(shù)： | 4/33頁 |
| 文件大?。?/td> | 313K |
| 代理商： | MK68901 |
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Figure 4 :
Register Map.
Address Port N
°
.
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
Abbreviation
GPIP
AER
DDR
IERA
IERB
IPRA
IPRB
ISRA
ISRB
IMRA
IMRB
VR
TACR
TBCR
TCDCR
TADR
TBDR
TCDR
TDDR
SCR
UCR
RSR
TSR
UDR
Register Name
GENERAL PURPOSE I/O
ACTIVE EDGE REGISTER
DATA DIRECTION REGISTER
INTERRUPT ENABLE REGISTER A
INTERRUPT ENABLE REGISTER B
INTERRUPT PENDING REGISTER A
INTERRUPT PENDING REGISTER B
INTERRUPT IN-SERVICE REGISTER A
INTERRUPT IN-SERVICE REGISTER B
INTERRUPT MASK REGISTER A
INTERRUPT MASK REGISTER B
VECTOR REGISTER
TIMER A CONTROL REGISTER
TIMER B CONTROL REGISTER
TIMERS C AND D CONTROL REGISTER
TIMER A DATA REGISTER
TIMER B DATA REGISTER
TIMER C DATA REGISTER
TIMER D DATA REGISTER
SYNC CHARACTER REGISTER
USART CONTROL REGISTER
RECEIVER STATUS REGISTER
TRANSMITTER STATUS REGISTER
USART DATA REGISTER
INTERRUPTS
The General Purpose I/O-Interrupt Port (GPIP) pro-
vides eight I/O lines that may be operated either as
inputsoroutputs under softwarecontrol. Inaddition,
each line may generate an interrupt in either a po-
sitivegoing edge ora negative goingedge ofthe in-
put signal.
The GPIP has three associated registers. One al-
lows theprogrammer to specify the Active Edgefor
each bitthat willtrigger aninterrupt. Anotherregister
specifies the Data Direction (input or output) asso-
ciated with each bit. The third register is the actual
data I/O register used to input or output data to the
port. These three registers are illstrated in figure 5.
The Active Edge Register (AER) allows each of the
General Purpose Interrupts to provide an interrupt
on eithera 1-0 transition ora 0-1 transition. Writing
a zeroto the appropriate bit of the AERcauses the
associated input to produce an interrupt on the 1-0
transition. The edge bit is simply one input to an ex-
clusive-orgate, withtheother input comingfrom the
input buffer ant the output going to a 1-0 transition
detector. Thus, depending upon the state of the in-
put, writing the AER can cause an interrupt-produ-
cing transition, which will cause an interrupt on the
associated channel, if that channel is enabled. One
would then normally configure the AER before
enabling interrupts via IERA and IERB.
Note : Changing the edge bit, with the interrupt
enabled, may cause an interrupt on that channel.
TheData Direction Register (DDR)isusedtodefine
10-17 as inputs or as outputs on a bit by bit basis.
Writing a zero into a bit of the DDRcauses the cor-
responding Interrupt-I/O pin to be a Hi-Z input. Wri-
ting a one into a bit of the DDR causes the cor-
responding pin to be configured as a push-pull out-
put. When data is written into the GPIP,those pins
defined as inputs will remainin theHi-Z state while
those pins defined as outputs willassume thestate
(high or low) of theircorresponding bit inthe GPIP.
When the GPIP is read, the data read will come di-
rectlyfromthecorresponding bitofthe GPIPregister
for allpins defined as output, whilethe data read on
all pins defined as inputs will come from the input
buffers.
Each individual function inthe MK68901 isprovided
withauniqueinterruptvectorthatispresentedtothe
systemduring theinterrupt acknowledge cycle.The
interrupt vector returned during the interrupt ac-
knowledge cycleis shownin figure 6, while the vec-
tor register is shown in figure 7.
MK68901
4/33
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