參數(shù)資料
型號(hào)： MK68901
廠(chǎng)商： 意法半導(dǎo)體
英文描述： Multifunction Peripheral(多功能外圍電路)
中文描述： 多功能外圍（多功能外圍電路）
文件頁(yè)數(shù)： 13/33頁(yè)
文件大?。?/td> 313K
代理商： MK68901
A isreprogrammed for another mode, interrupts will
againoccuronthe transition,as normally defined by
the edge bit. Note that, like changing the edge bit,
placing the timer into or taking it out of the pulse
width mode can produce a transition on the signal
to theinterrupt channeland may causean interrupt.
If measuring consecutive pulses, it is obvious that
one mustread the contentsofthetimerandthenrei-
nitialize the maincounter bywriting tothetimerdata
register. If the timer data register is written while the
pulse isgoing to theactive state, the write operation
may result in an indeterminate value being written
into themain counter. If the timer is written after the
pulse goes active, the timer counts from the pre-
vious contents, and when it counts through H”01”,
the correct value is written into the timer. The pulse
width then includes counts from before the timer
was reloaded.
In theevent count mode, the prescaler is disabled.
Each timethe control input on TAI or TBimakes an
activetransition as defined by the associated Inter-
rupt Channel’s edge bit, a count pulse will be gene-
rated, and the main counter willdecrement. In all o-
ther respects, the timerfunctionsas previously des-
cribed. Altering the edge bit while the timer is in the
event count mode can produce a countpulse. The
interrupt channel associated with the input (I3 for I4
for TAI) is allowed to function normally. To count
transitions reliably, the input must remain in each
state (1/O) for a length of time equal to four periods
of thetimer clock ; thus signals of a frequency up to
one fourth of thetimer clock canbe counted.
The manner in which the timer output pins toggle
states has previously been described. All timerout-
puts will be forced lowby a device RESET. The out-
put associated with Timers A and B will toggle on
each Time Out pulse regardless of the mode the ti-
mers are programmed to. In addition, the outputs
from TimersA and B can be forced low at any time
by writing a ”1” to the reset location in TACR and
TBCR, respectively. The output will be forced to the
low state during the WRITE operation, and at the
conclusion of theoperation, the output will again be
free to toggle each time a Time Out pulse occurs.
Thisfeature will allow waveform generation.
During reset,theTimerData Registers andthemain
countersare not reset. Also,ifusing thereset option
on Timers A or B, one must make sure to keep the
other bits in the correct state so as not to affectthe
operation of Timers A and B.
USART
Serial Communication is provided by a full-duplex
double-buffered USART,which is capable of either
asynchronous or synchronous operation. Variable
word length and start/stop bit configurations are
available under software control for asynchronous
operation. Forsynchronous operation, aSync Word
is provided to establish synchronization during re-
ceive operations. TheSyncWord willalso berepea-
tedly transmitted when noother data is available for
transmission. Moreover, the MK68901 allows strip-
ping of all Sync Words received in synchronous o-
peration.Thehandshake controllinesRR(Receiver
Ready) and TR (Transmitter Ready) allow DMA o-
peration. Separate receive and transmit clocks are
available, and separate receive and transmit status
and data bytes allow independent operation of the
transmit and receive sections.
The USART is provided with three Control/Status
Registers and a Data Register. The USART Data
Register form is illustrated in figure 16. The pro-
grammer may specify operational parameters for
theUSARTviatheControl Register,asshowninfig-
ure 17. Status ofboth the Receiver andTransmitter
sectionsisaccessedbymeansofthetwoStatusRe-
gisters, as shown in figures 18 and 19. Data written
to the Data Register is passed to the transmitter,
while reading the DataRegister will access data re-
ceived by theUSART.
Figure 16 :
USART Data Register.
V000362
MK68901
13/33
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